Altera Corporation

Apple Inc.

Lsi Corporation

Wing Liu

Sanjeev K Maheshwari

Lizhi Zhong

Wenbo Liu

Vishal Varma

Gary A Rogan

Jaeduk Han

Sunil Bhosekar

Ming-Shuan Chen

Freeman Yingquan Zhong

Mei Luo

Eric M Zhang

A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.

Receiver with half-rate sampler circuits

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Serial data receiver with sampling clock skew compensation

An integrated circuit is disclosed. The integrated circuit includes an equalizer circuit that may provide high-frequency signal amplification. The equalizer circuit also has adjustable impedance circuitry, which may receive digital control signals to adjust the effective impedance of the equalizer circuit. Furthermore, a method of operating the equalizer circuit is also disclosed.

Equalizer circuitry having digitally controlled impedances

One embodiment relates to an apparatus for regulating a voltage-controlled oscillator. The apparatus includes a digital-to-analog converter that has an input that receives a digital input signal and an output that outputs an analog control signal. A transistor receives the analog control signal so as to control an output voltage of the voltage-controlled oscillator. Control circuitry receives the output voltage and generates the digital input signal. Another embodiment relates to a method of regulating a voltage-controlled oscillator. A digital input signal is converted to an analog control signal using a digital-to-analog converter. The output voltage of the voltage-controlled oscillator is controlled using the analog control signal and monitored using a plurality of comparators. The digital input signal is changed depending on outputs of the plurality of comparators. Other embodiments, aspects, and features of the invention are also disclosed.

Low-noise voltage regulator for voltage-controlled oscillator

One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal amplitude. The second average signal amplitude may be an average signal amplitude of a high-frequency portion of the equalized signal. Other embodiments and features are also disclosed.

Apparatus and methods for equalizer adaptation

In an embodiment of the present invention, a feedback technique is used to track a reference signal with a DFE summing node common mode voltage. For example, in an embodiment implemented in CML, the feedback signal shifts both differential signals (e.g., the summing node common voltage and the reference voltage) by the same amount. In such an embodiment, the feedback technique preferably changes the reference common mode but not its differential mode.

Apparatus and method for common mode tracking in DFE adaptation

An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

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Milpitas, CA, United States of America

Wing Liu