International Business Machines Corporation

Infineon Technologies Ag

Wing Kin Luk

Robert H Dennard

Leland Chang

John Atkinson Fifield

Toshiaki Kirihata

Robert K Montoye

Philip George Emma

Stephen Victor Kosonocky

Wei Hwang

Vijayalakshmi Srinivasan

David Michael Fried

Brian L Ji

Thomas R Puzak

Daniel W Storaska

Roy E Scheuerlein

Daniel Joseph Friedman

Ravi Nair

Jin Cai

William Robert Reohr

Russell J Houghton

Yasunao Katayama

Gerhard Mueller

Jeremy K Stephens

Yong Liu

Donald T Tang

Wilm Ernst Donath

Brian L Li

Toshiaki Kirihara

A gated diode memory cell is provided, including one or more transistors, such as field effect transistors ('FETs'), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline ('BL') and the gate of the first FET being in signal communication with a write wordline (&#x201c;WLw&#x201d;), and the source of the gated diode being in signal communication with a read wordline (&#x201c;WLr&#x201d;).

Gated diode memory cells

A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.

Amplifiers using gated diodes

A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.

Method and system for providing an improved store-in cache

A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

Dynamic memory cell structures

A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.

Low voltage signaling

A low-swing receiver includes a sense amplifier including a first transistor having a source connected with a first voltage supply and a gate for receiving a control signal, and a second transistor having a source connected with a second voltage supply, a drain connected to a drain of the first transistor, and a gate coupled to a second control signal via a capacitive element. A switching circuit is operative to selectively couple an input signal supplied to the sense amplifier with the gate of the second transistor as a function of a signal generated at an output of the sense amplifier. The sense amplifier is operative in a first mode to store charge in the capacitive element, and is operative in a second mode to impart a voltage on the gate of the second transistor which is indicative of the charge stored in the capacitive element.

Low-swing signaling scheme for data communication

A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.

An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.

Area-efficient gated diode structure and method of forming same

Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus improving cache availability and reducing power compared to conventional DRAM caches. Compared to existing SRAM caches, the new cache structures can potentially achieve the same (or better) speed, lower power and better tolerance to chip process variations in future process technologies.

DRAM Cache with on-demand reload

A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output.

Multi-port dynamic memory methods

A dynamic random access memory circuit has at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, and a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line.

Growing community of inventors

Chappaqua, NY, United States of America

Wing Kin Luk