Cadence Design Systems, Inc.

Wing-Kai Chow

Mehmet Can Yildiz

Gracieli Posser

Zhuo Li

Wen-Hao Liu

Charles Jay Alpert

Derong Liu

Mateus Paiva Fogaça

Hongxin Kong

Yi-Xiao Ding

Various embodiments provide for pin access location generation for one or more cells of a circuit design, which may be part of electronic design automation (EDA). Some embodiments facilitate pin access location generation by generating and using multiple graphs, which enable such embodiments to ensure that neighbor pins are not missed and to check for design rule violations.

Cell-based pin access location generation

Aspects of the present disclosure address systems and methods for timing-based layer assignment. Routing is performed on a set of nets of an integrated circuit design. The routing comprises generating a route between a first pin and a second pin of a net. An initial layer assignment is performed on the set of nets based on the routing. The initial layer assignment comprises assigning the route to a first layer of the design based on first preferred routing layer designation. Timing-based layer assignment is performed based on the initial layer assignment. The timing-based layer assignment comprises reassigning the route from the first layer to a second layer based on a second preferred routing layer designation determined based on a comparison of a first delay value associated with the first layer and a second delay value associated with the second preferred routing layer designation.

Timing-based layer assignment

Aspects of the present disclosure address systems and methods for density-aware layer assignment for integrated circuit (IC) designs. Data describing an IC design is accessed. The IC design comprises a net and a set of routing layers. Single-layer routing and an initial layer assignment is performed on the set of nets. The single-layer routing and the initial layer assignment comprises generating a route for a net from the set of nets and assigning the route to one or more layers from the set of layers. A multi-layer density map is generated based on the single-layer routing and the initial layer assignment on the set of nets. Incremental layer reassignment is performed on the set of nets based on the multi-layer density map. The incremental layer assignment comprises reassigning a segment of the route from the first layer to a second layer from the set of layers based on the density value.

Wire density-aware layer assignment

Aspects of the present disclosure address systems and methods for zigzag detection and handling for integrated circuit designs. Data describing an integrated circuit is accessed. The integrated circuit design comprises a connection path between two or more pins of a net determined based on an initial routing of the net. A zigzag is detected in the connection path based on a local turn density constraint that specifies a ratio of a number of turns to a pathlength that corresponds to zigzagging in the net. In response to detecting the zigzag in the connection path, the zigzag is removed from the connection path by rerouting the net using a routing constraint that defines a maximum number of turns in the connection path.

Zigzag detection and handling for integrated circuit design

Aspects of the present disclosure address systems and methods for routing an integrated circuit design based on a maximum turn constraint. Data describing an integrated circuit is accessed. The integrated circuit design comprises a net specifying a connection between a first pin and a second pin. A maximum turn constraint is accessed. The maximum turn constraint specifies a maximum number of turns for connection paths generated in routing the integrated circuit design. The net is routed based on the maximum turn constraint. The routing of the net results in a routed net comprising a connection path between the first pin and the second pin that includes a number of turns that satisfy the maximum turn constraint. A layout instance for the integrated circuit design is generated based in part on the routed net.

Maximum turn constraint for routing of integrated circuit designs

Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping routing regions are routed at the same time, and such that idle time of each thread (e.g., time where thread has no work or is waiting for another thread to finish) can be minimized.

Multi-threaded network routing based on partitioning

Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Circuit design routing based on routing demand adjustment

Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in routing blockage of the circuit design. For example, the parameter can control how much detour is acceptable when handling routing for a pin inside a routing blockage.

Routing based on pin placement within routing blockage

Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Routing congestion based on layer-assigned net and placement blockage

Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Routing congestion based on via spacing and pin density

Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.

Clock pin to clock tap assignment based on circuit device connectivity

Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

Circuit design routing based on parallel run length rules

Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

Integrated circuit routing based on enhanced topology

Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is 'entry-aware' in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

Routing framework to resolve single-entry constraint violations for integrated circuit designs

Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

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Austin, TX, United States of America

Wing-Kai Chow