Intel Corporation

Marvell International Limited

Legerity, Inc.

Wing K Yu

Nigel C Paver

Murli Ganeshan

Mark Norman Fullerton

Stephen J Strazdus

Mukesh Patel

Rupal Parikh

William T Maghielse

Jianwei Liu

Anthony Jebson

Deli Deng

Kailesh B Bavaria

Digitally controllable delay lines including fine grain and coarse grain delay elements, and methods and system to calibrate the delay lines in fine grain increments. Calibration may include calibrating a number of fine grain elements for which a combined delay is substantially equal to a delay of a coarse grain element, and calibrating numbers of fine grain and coarse grain elements which a combined delay corresponds to a period of a reference clock. A digitally controlled delay line may be implemented as part of a digital delay locked loop (DLL), and calibration parameters may be provided to a slave DLL having a similarly implemented delay line. A digitally controllable DLL may provide relatively low-power, high-resolution over a spectrum of process, voltage, and temperature variations, and may be implemented in relatively high-speed applications previously reserved for analog DLLs.

Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a coprocessor targetted by the coprocessor instructions. After determining whether to alternatively load source values into a respective one of two source registers, new source values are transferred to one or more of the source registers. The coprocessor executes the coprocessor instruction, which includes an offset information, to extract values from the source registers based on the offset information and places the values in a destination register.

Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type. A source register in the main processor and a destination register is in the coprocessor, those registers including data elements. The coprocessor instruction includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction, the instruction to broadcast a data element from said source register to said destination register.

Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Conditional execution of coprocessor instruction based on main processor arithmetic flags

The present invention is directed to a method and arrangement for phase-locking to an incoming signal using a fast-acting start-up mode followed by a second steady-state mode of operation. The method includes providing a reference signal by dividing the incoming signal by m during a phase-lock initiation stage and by dividing by n thereafter, providing an output signal having a frequency that is synchronized to the incoming signal when the arrangement is phase-locked to the incoming signal, and providing a feedback signal by dividing the output signal by x during a phase-lock initiation stage and by dividing by y thereafter. A phase difference between the feedback and reference signals is detected and the frequency-controllable oscillator is controlled, so that the frequency of the output signal is synchronized to the incoming signal.

Phase-locked loop arrangement with fast lock mode

A memory may include sectional columns so that groups of cells on the same column but coupled to different word lines may be selectively accessed. As a result, only a portion of the cells of a given column is activated at any given time. The remainder of the column may be decoupled, thereby reducing the need to charge up or discharge the rest of the column. Because only a smaller portion of the column is charged or discharged, the lower capacitance associated with a lower number of cells may result in a speed and power consumption improvement.

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Chandler, AZ, United States of America

Wing K Yu