Agilent Technologies, Inc.

Keysight Technologies, Inc.

Wing J Mar

Joseph Michael Gorin

Hassan Tanbakuchi

Reto Zingg

Wim Cresens

Sebastien Louveaux

Douglas Gordon Yule, Jr

Thomas M Wright

Gregory B Korelich

A phase lock loop (PLL) includes a phase detector configured to output a signal indicative of a phase difference between a reference signal and a feedback signal, a loop filter configured to filter an output of the phase detector, and a voltage-controlled oscillator (VCO) configured to output an oscillating signal having a frequency corresponding to an output of the loop filter. The PLL further includes a frequency divider configured to output the feedback signal by frequency dividing the oscillating signal output by the VCO, and a reset circuit configured to reset the frequency divider in an initialization mode such that a phase difference between the reference signal and the feedback signal corresponds to a lock angle of the PLL.

Phase lock loops (PLLS) and methods of initializing PLLS

A signal processor includes a frequency generator that employs a direct digital synthesizer (DDS) to generate a first local oscillator (LO) signal with a variable first LO frequency. The signal processor also includes an oscillator generating a second LO signal having a second LO frequency. The DDS employs programmable frequency control word and a sampling clock signal having a variable sampling clock frequency that is derived from the second LO frequency, to generate a DDS output signal from which the first LO signal is produced. The variable sampling clock frequency and the programmable frequency control word are selected to avoid crossing spurs in the frequency spectrum of the DDS output signal.

Frequency generator including direct digital synthesizer and signal processor including the same

A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.

Frequency generator and method of frequency generation with multiple sampling phase detectors

A measurement technique that provides a full solution to the gated local oscillator sweep measurement and improves the accuracy of signal analyzers in gated sweep mode by pre-sweeping the local oscillator at the beginning of a gate pulse and over-sweeping the local oscillator at the end of each gate pulse.

Gated sweep in spectrum analyzers

A vector network analysis system and a method of measuring use offset stimulus signals to stimulate a balanced device under test (DUT) to determine performance parameters. The system includes an offset stimulus source that provides a plurality of stimulus signals and a vector network analyzer. At least one stimulus signal is offset from another stimulus signal of the plurality in one or both of frequency and time-varying phase. The offset stimulus source includes a first signal source and a second signal source that respectively provides the offset stimulus signals. The method of measuring includes generating the offset stimulus signals and applying the offset stimulus signals to a balanced port of the DUT to stimulate the DUT. The performance parameters are determined from measurements of the offset stimulus signals and one or more response signals from the stimulated DUT.

Vector network analysis system and method using offset stimulus signals

This invention adds a non-linear sweep accumulator to the conventional sigma-delta fractional-N divider to produce a N.F value that is a polynomial function of time. This allows any non-linear sweep profiles to be approximated.

Fractional-N divider configurable as a polynomial function for real-time PLL swept frequency applications

An adaptive cycle-slipped detector ('ACSD') for use in a Phase-Locked Loop ('PLL') circuit. The ACSD may include a phase comparator, a phase shifter in signal communication with the phase comparator, and a cycle-slipped detector (&#x201c;CSD&#x201d;) in signal communication with the phase shifter.

Adaptive cycle-slipped detector for unlock detection in phase-locked loop applications

A method and apparatus compensates for phase noise added by a spectrum analyzer from phase noise measurements of a signal under test (SUT) taken by the spectrum analyzer. The method comprises the steps of measuring the phase noise of the SUT, determining the added phase noise of the spectrum analyzer, and applying a mathematical correction to the measured phase noise. A spectrum analyzer apparatus that compensates for added phase noise comprises a controller portion, a memory portion, a signal conversion and detection portion, and a compensation algorithm stored in the memory portion. A system that compensates for added phase noise comprises a controller having a control algorithm and a spectrum analyzer. The compensation and control algorithms are computer programs that implement the method of the present invention.

Phase-noise measurement with compensation for phase noise contributed by spectrum analyzer

A signal synthesizer includes a high frequency offset stage having a high frequency offset source and frequency translation element in the feedback path of a dual-oscillator offset loop synthesizer. The signal synthesizer achieves low phase noise via noise cancellation when used to provide the first local oscillator of a spectrum analyzer and when the second local oscillator of the spectrum analyzer provides the high frequency offset source to the signal synthesizer.

Dual-oscillator signal synthesizer having high frequency offset stage

A direct frequency synthesizer provides an output signal derived from a high frequency reference signal that is frequency divided and mixed to satisfy the coarse step synthesis requirements of an offset loop synthesizer. The absence of a VCO within the direct frequency synthesizer, provides the direct frequency synthesizer with lower phase noise than a typical PLL-based coarse step synthesizer. Though applicable to a variety of types of synthesizers and signal generators, the direct frequency synthesizer provides especially advantageous noise performance when used to generate an offset signal for an offset loop synthesizer of the first local oscillator of a spectrum analyzer, where the second local oscillator of the spectrum analyzer provides the reference signal for the direct frequency synthesizer.

Direct frequency synthesizer for offset loop synthesizer

A frequency synthesizer that includes an output oscillator, a difference circuit, a reference circuit, a feedback circuit and a comparator. The output oscillator generates an output signal whose frequency, F , is determined by an oscillator input signal. The difference circuit generates a sampled signal having a frequency, F &equals;F &minus;F . The reference circuit generates a reference signal having a frequency F . The reference circuit includes a reference oscillator for generating a high frequency reference oscillator output signal having a frequency F and a first division circuit for generating a signal having a frequency equal to F divided by R. The feedback circuit generates a feedback signal having a frequency, F . The feedback signal generating circuit includes a second division circuit having a division factor chosen such that F /F is minimized. The comparator compares the reference signal and the feedback signal and generates the oscillator input signal. One of the first and second division circuits is a Fractional-N Divider having a division factor, N.F, greater than 10. If the second division circuit is the Fractional-N Divider, the feedback circuit includes a multiplication circuit for generating a multiplied signal having a frequency equal to X times F , and the Fractional-N Divider generates the feedback signal from the multiplied signal. In the preferred embodiment of the present invention, the first division circuit is the Fractional-N Divider. In one embodiment of the invention, the input to the Fractional N Divider varies over time thereby causing the output oscillator to sweep through a corresponding frequency range.

High performance microwave synthesizer using multiple-modulator fractional-N divider

A phase noise measurement module (PNMM), system and method for measuring phase noise improve accuracy of phase noise measurements of a signal under test (SUT) using a spectrum analyzer. The PNMM includes an RF to hF frequency converter and a selectable frequency divider. The system includes the PNMM connected to the spectrum analyzer and employs an LO signal from a tunable LO in the spectrum analyzer. The method includes directly converting an input SUT to an IF signal having either a second or a third IF frequency that is applied to a corresponding frequency conversion stage of the spectrum analyzer before the phase noise is measured. The present invention bypasses a first conversion stage, and typically a second conversion stage as well, of the spectrum analyzer and directly converts the SUT to either the second or third IF frequency, thereby reducing phase noise added to the SUT.

Phase noise measurement module and method for a spectrum analyzer

A microwave synthesizer apparatus features very low phase noise, fine frequency resolution and wide tuning range coverage. The microwave synthesizer apparatus utilizes a fundamental offset source in an offset phase lock loop (PLL) to translate an output signal Fout to a lower IF signal Fif for locking to a low frequency interpolation signal Fint. The use of the fundamental offset source instead of the conventional multiple frequency offset signal from a comb generator or sampler results in superior phase noise and spurious performance. The synthesizer comprises a main signal loop having a main loop VCO that produces an output signal Fout and an offset signal loop having an offset VCO that produces an output signal Fos. The signals Fos and Fout are mixed in the main loop to control the frequency of the signal Fout. The main loop VCO and the offset loop VCO preferably are YIG-tuned Oscillators (YTOs) that share a main coil. Moreover, the main YTO and the offset YTO preferably have a common housing and further, each of the main YTO and the offset YTO has a separate FM coil. The use of a dual YTO in the microwave synthesizer apparatus minimizes overall cost and power consumption of the synthesizer by combining the dual YTO in the single package. In one embodiment, the microwave synthesizer further comprises a mode selection feature that selects between operation of the synthesizer in an offset or dual loop mode and a variable divider or single loop mode. In another embodiment, the microwave synthesizer further comprises a selectable frequency divider that produces the output signal Fos with a smaller frequency step size.

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Rohnert, CA, United States of America

Wing J Mar