Zoran Corporation

Ati Technologies Ulc

Ati Technologies Inc.

Ati International Srl

Wing-Chi Chow

Vladimir F Giemborek

Aharon Gill

Pasquale Leone

Yung-Jung Wayne Wu

James C Yee

Stuart J Lindsay

Techniques described herein allow multi-pass writeback processing of graphical frames (such as those having a high or ultrahigh resolution) to reduce bandwidth for display operations by, for example, splitting an input stream for processing by separate graphical pipelines as two or more spatially segmented portions. After receiving a graphical frame for processing, the graphical frame is spatially segmented into multiple portions. Each of the multiple portions is provided to a respective graphical pipeline of a plurality of graphical pipelines for processing. Each processed portion of the graphical frame is written substantially simultaneously to a corresponding portion of a system memory.

Multi-pass writeback with single-pass display consumption

In response to a video aspect ratio of a frame of video not matching an aspect ratio of a display panel of a display device, a source device of a processing system transmits only the frame to the display device and metadata indicating that the display device is to generate bars for letterboxing or pillarboxing. By generating the bars for letterboxing or pillarboxing at the display device instead of transmitting the bars from the source device to the display device or storing the bars at a frame buffer of the display device, the processing system conserves power and bandwidth.

Video frame transport

A programmable digital data encoder employs error correcting coding that uses Galois field multiplication logic wherein each bit of the product is produced by first applying pre-calculated mask values or mask values calculated via a processor executing code, and then applying an XOR circuit together with the mask bits from the pre-calculated or generated mask. In one example, a set of Galois field multipliers is used wherein each multiplier in the set includes a plurality of 2-bit input AND gate circuits and an m-bit input XOR gate circuit to produce a bit of the product. In one example, there are 'm' mask values in a mask table wherein m is the symbol width. A different mask value is applied for each bit of the product. The mask values are each m-bits wide, and are stored, for example, in memory as a small look-up table with m m-bit entries or in m m-bit wide registers.

Encoder with mask based galois multipliers

A unique method for chroma vertical upsampling used, for example, for conversion of the '4:2:0' format chroma information used in many applications of digital video, to the '4:2:2' or &#x201c;4:4:4&#x201d; format, is presented. This conversion is required so that video encoders can effect the display of this chroma information with a minimum of visible artifacts. The present invention carries out chroma vertical upsampling on a pixel by pixel basis. This chroma vertical upsampling is performed as a function of the amount of motion associated with each pixel as detected between 2 or more fields, and the field, frame and progressive sequence characteristics of the incoming video signal data.

Chroma upsampling method and apparatus therefor

Improved 2:2 and 3:2 pull-down detection techniques are presented. These techniques can, for example, be used when converting an interlaced video signal into a progressive video signal. The improved techniques are less susceptible to bad edits. In one embodiment, comparison values are generated using consecutive fields of the interlaced video signal having the same parity, with a sequence of one small comparison value followed four large comparison values, where the four large comparison values include two pairs of similar large comparison values, is used to indicate a 3:2 pull-down.

2:2 and 3:2 pull-down detection techniques

A technique for determining the slope of a field pixel is described. According to the technique, one or more sets of diagonal field pixels are downscaled (or downsampled) before they are provided to respective edge detector circuits. By downscaling the sets of diagonal field pixels before they are provided to respective detector circuits, the edge detector circuits detect diagonal edges and, in particular, shallow diagonal edges with greater accuracy. As such, the slopes assigned to the field pixels are more likely to be correct. This ultimately results in a high quality progressive video signal that can be used to generate an image that is completely or substantially free from objectionable artifacts.

Technique for determining the slope of a field pixel

A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.

Bus mastering interface control system for transferring multistream data over a host bus

A universal asynchronous receiver transmitter (UART) emulation stage for modem communication uses a digital signal processor containing a software UART control program for sending UART control signals to hardware based UART emulation circuitry. The software UART control program communicates to a modem application interface program that is under control of a host processor. The UART emulation circuitry that is responsive to the control signals from the digital signal processor, includes dedicated transmit and receive FIFO buffer memory for storing modem data and also includes interrupt generation logic to generate an interrupt for the digital signal processor when the received FIFO buffer memory is at a predetermined threshold. The UART emulation circuitry also includes programmable control logic for facilitating host processor interrupt pacing to maintain high compatibility with legacy applications, namely DOS based applications.

Universal asynchronous receiver transmitter (UART) emulation stage for modem communication

The invention features a method and apparatus for use with a computer system having a memory and a bus (e.g., a PCI bus). The bus is monitored for detection of a bus cycle intended for a controller (e.g., a DMA controller) used to transfer data between a bus device and the memory. After detection, the bus device is used to claim the bus cycle and to emulate the response of the controller to the bus cycle.

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Toronto, Canada

Wing-Chi Chow