Brocade Communications Systems, Inc.

Intel Corporation

Barracuda Networks, Inc.

Brocade Communication Systems LLC

Avago Technologies International Sales Pte. Limited

Wing Cheung

John Michael Terry

Surya Parkash Varanasi

Suresh Vobbilisetty

Jian S Liu

Phanidhar Koganti

Anoop Ghanwani

Daniel Christian Biederman

Shunjia Yu

Robert G Hathaway

Mythilikanth Raman

Rajiv Krishnamurthy

Joseph Juh-En Cheng

Parviz Ghalambor

Jose Niell

Philip Lynn Leichty

Mahesh Srinivasa Maddury

Jan Bialkowski

Matthew James Webb

Dilip Chatwani

How Tung Lim

Chih-Jen Chang

Surya Prakash Varanasi

Nagarajan Venkatesan

Kung Ling Ko

A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

Processor related communications

Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

Preserving quality of service across trill networks

One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

Method and system for link aggregation across multiple switches

A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.

Longest prefix match scheme

A solution for network packet latency measurement includes, at a network device having a memory, storing a first time value indicating when an ingress port of the network device received a packet. The solution also includes storing a second time value indicating when an egress port of the network device received the packet for transmission towards another network device. The solution also includes storing a difference between the first time value and the second time value.

Network packet latency measurement

An interconnect switch stores data messages received from one or more source devices and prioritizes the data messages received from each source device based on the order that the data messages were received from the source device. For each available destination device associated with the interconnect switch, the interconnect switch identifies the data messages with the highest priority that are to be routed to the available destination device and selects one of the identified data messages for the available destination device. The interconnect switch then routes the selected data messages to the available destination devices.

Method and system for a multi-stage interconnect switch

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Fremont, CA, United States of America

Wing Cheung