Eastman-kodak Company

Win-Chyi Chang

Ram Kannegundla

Constantine N Anagnostopoulos

Stephen L Kosman

Georgia R Torok

Eric Gordon Stevens

Teh-Hsuang Lee

Bruce C Burkey

By incorporating an ITO electrode which is more transparent than polysilicon, and designing the pixel such that it has asymmetric gates with as much as possible of its light sensitive region covered by an ITO electrode, light sensitivity is increased. To solve the problem of impurity diffusion from the ITO electrode into the silicon below, the conventional Silicon Dioxide gate dielectric was replaced with an Oxide/Nitride/Oxide stack. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO. The pixel light sensitivity improves not only because the light passes through the more transparent ITO electrode, but also because some of the light that would have fallen on the LOD region and would be lost, is now collected. The second method is for color CCD sensors with color filter patterns, such as the 'BAYER' color filter pattern to name just one, to have the overlap of the color filters, which does not allow light transmission, to occur over the less sensitive area of the pixel, which is the area covered with the polysilicon electrode. For proper operation a slight modification of the vertical clock timing is needed.

Method of fabricating a image sensor having ITO electrodes with

By designing pixels with highly transparent ITO electrodes and asymmetric gates such that as much light as possible falls upon a region covered by an ITO electrode, light sensitivity is increased. Impurity diffusion from the ITO electrode into the silicon below is prevented by employing an Oxide/Nitride/Oxide stack as a dielectric. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO. The second method is for color CCD sensors with color filter patterns, such as the 'BAYER' color filter pattern to name just one, to have the overlap of the color filters, which does not allow light transmission, to occur over the less sensitive area of the pixel, which is the area covered with the polysilicon electrode. For proper operation a slight modification of the vertical clock timing is needed.

Image sensor having ITO electrodes with overlapping color filters for

An apparatus for capturing an image in accordance with the invention includes a full frame charge coupled device with a photosensitive layer and a mask covering a portion of said photosensitive layer with a plurality of apertures. The apparatus also includes an exposure controller for controlling the exposure of the photosensitive layer to the image to be captured and also a shifter for shifting either the image or the full frame charge coupled device to expose a different portion of the image to the photosensitive layer through the apertures. With this invention, a high resolution image can be captured with a full frame CCD image sensor, without loss of resolution. As a result, a lower cost imaging apparatus can be obtained without loss of resolution.

Integrated apertures on a full frame CCD image sensor

A timing logic system which includes a generic television-standard timing generator selectably provides precisely timed horizontal and vertical control signals for controlling the operation of a high resolution charge coupled device (CCD) image sensor of the type having two line pixel registers in a high resolution mode of picture imaging. Alternatively, the timing logic system selectably provides precisely timed horizontal and vertical control signals, and a precisely timed display field control signal applied to a switch mechanism, for controlling the operation of the high resolution CCD image sensor in a television resolution mode of picture imaging in accordance with a television standard, for example, the NTSC standard. The timing logic system also provides sync and control signals to a television-standard display in the television mode of operation. In both the high resolution mode and the television mode of operation, the timing logic system provides the respective horizontal and vertical control signals to the CCD image sensor so that both line pixel registers are operative.

Timing logic system and method for selectably controlling a high

Apparatus and method for controlling a high resolution charge coupled device (CCD) image sensor operate in accordance with a television standard to provide horizontal, vertical, and other CCD control signals to obtain a purely sequential high resolution mode of operation on the one hand. Alternatively, there is a modified mode of operation which provides interlaced even and odd groups of video signals to be viewed directly on a television viewfinder display. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to selectably generate the vertical, horizontal, and other CCD control signals for the alternate modes of operation. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate vertical, horizontal, and other CCD control signals.

Apparatus and method for controlling a high resolution charge coupled

Solid-state image sensors, in general, comprise a photodetector for detecting radiation from the image and converting the radiation to charge carriers, and transfer means for carrying the charge carriers to an output circuit. One type of solid-state image sensor uses a CCD as both the photodetector and the transfer means. The solid-state image sensor generally includes a plurality of the CCD's arranged in spaced parallel relation to form an array. The image sensor of this disclosure utilizes only one antiblooming lateral overflow barrier. The excess signal charge of phase 1 flows into the preceding phase 2 and is saved. This eliminates the overflow barrier of phase 1 so that blooming protection is via the overflow barrier of the preceding phase 2. This results in an image sensor with blooming protection and increased charge capacity.

Antiblooming structure for solid-state image sensor

A camera system and method of operation is disclosed which produces an NTSC type interlaced signal from a high resolution non-interlaced camera system by summing in a shift register first and second rows thereof and discarding via diodes on a charge coupled device (CCD) sensor chip third and fourth rows of every four rows of pixel information to produce odd fields of an interlaced signal. Even fields are produced by discarding the first and second rows and summing the third and fourth rows. Sync and blanking pulses may be added to complete the signal.

Apparatus and method for generating an interlaced viewing signal from

A low cost system for efficiently doubling the data readout rate from a high resolution CCD video sensor having two line outputs includes a pair of analog to digital converters, a separate pair of first-in first-out line stores for each of the analog to digital converters, and a digital to analog converter. Successive lines from the video sensor are fed into alternate ones of the analog to digital converters in sequence at the normal pixel clock frequency used with other than high resolution sensors. The contents of successive lines in each of the analog to digital converters are written into alternate ones of its respective pair of line stores in sequence. The contents of successive lines from all of the line stores are fed into the digital to analog converter. Finally, analog data is read out of the digital to analog converter to the single analog input of a high resolution video monitor at twice the pixel clock frequency. The entire system is made up of off-the-shelf components which are compact and relatively inexpensive.

Display interface for high resolution CCD video sensor

The present invention is a high resolution charge-coupled device (CCD) camera system having a CCD camera which is capable of operating at a low data rate (e.g., 1 to 2.5 MHz) that is compatible with the input data rate of a computer. An output of the CCD camera is coupled through an analog-to-digital converter (A/D) to an input of the computer which receives and analyzes the output of the camera. The CCD camera contains a CCD image sensor which is a two phase sensor capable of operating in a mode where holes are accumulated at room temperature so as to reduce the dark current generated in the sensor. Thus, the CCD camera system is of simple construction so as to be relatively inexpensive and can operate at room temperature with reduced dark current.

High resolution charge-coupled device (CCD) camera system

In a CCD in which a pixel is defined by at least two adjacent gate electrodes, voltages are applied to both gate electrodes to simultaneously place both gates of each pixel in a mode of operation whereby holes are accumulated at the surface of a substrate in which the CCD is formed. Preferably one of these voltages is at a higher potential level than the other.

Reducing dark current in charge coupled devices

A driver circuit, which is capable of operation in the 30 MHz frequency range and zero to +10 volts, is useful for driving charge coupled devices (CCDs). The driver circuit uses the parallel combination of an off the shelf bipolar integrated circuit capable of charging the CCD to about six volts and an off the shelf complementary field effect transistor transmission gate capable of charging the CCD to about +10 volts. The bipolar integrated circuit is capable of discharging the CCD from about +10 volts to zero volts (ground).

High voltage high speed CCD clock driver

A method is disclosed for testing a charge-coupled device (CCD). A test device for use in the method includes a buried channel transistor which is formed adjacent the CCD. The source and drain of the transistor are located on opposite sides of the CCD. In the use of the test device to locate barriers and pockets in the CCD, clock voltages that are used in the operation of the CCD are applied to the gate electrodes of the CCD to simulate the transfer of charge from one phase to another. Predetermined voltages are then applied to the transistor, and the drain current and source voltage are measured in order to construct curves which indicate the existence and size of the barriers and pockets.

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Penfield, NY, United States of America

Win-Chyi Chang