Mindspeed Technologies, Inc.

Conexant Systems, Inc.

Macom Technology Solutions Holdings, Inc.

Wim F Cops

Charles E Chang

Bo Zhang

Cristiano Bazzani

Daniel Draper

Daryush Shamlou

Daniel Schoch

Atul Gupta

Guang-Ming Yin

Raed Moughabghab

Jerome Garez

Naser Adas

Brian Hostetter

Yihai Xiang

Daryash &ldquo;Danny&rdquo; Shamlou

A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.

Variable clock phase generation method and system

A system and method for calculating optimal equalizer coefficients during an initialization phase is disclosed. An equalizer system for processing a received signal at a communications receiver comprises several equalizers and adaptation modules. A first equalizer is configured to receive and process a received signal to create a first equalizer output. The first equalizer is active during an initialization phase and active during an operational phase. A second equalizer is configured to receive and process the first equalizer output to create a second equalizer output. The second equalizer is active during an initialization phase and aids in the generation of the first equalizer coefficients, and inactive during an operation phase. A third equalizer is configured to receive and process the first equalizer output to create a third equalizer output such that the third equalizer is inactive during an initialization phase and active during an operation phase.

Equalizer for high speed serial data links and method of initialization

There is provided a voltage mode push-pull driver output stage with low power consumption and improved output return loss (ORL) suitable for various high bandwidth data transmission applications. By structuring the output stage to have tunable resistances adjustable by voltages applied to transistors, the output stage is readily adaptable to different applications requiring different resistances or impedance matching.

Voltage mode push-pull driver output stage with tunable resistances

Various systems and methods are provided for adaptive equalization. The adaptive equalization is performed on a data signal received from a channel in a receiver. The data signal is equalized using an equalizer in the receiver, thereby generating an equalized data signal. During equalization, an equalization setting of the equalizer is adapted based upon an overshoot of the equalized data signal at a data transition.

Adaptive equalization based on signal overshoot

Disclosed in various embodiments are a circuit and method for driving a signal. In one embodiment, the circuit includes a passive impedance conversion network and at least two signal drivers coupled to the passive impedance conversion network. Each of the signal drivers includes a signal input coupled to a common signal input node.

Impedance conversion in data communication

Various systems and methods for automatic data rate detection are provided. In one embodiment, a system is provided that includes a clock and data recovery circuit embodied in a first integrated circuit, the clock and data recovery circuit being configured to re-clock a data stream. The system also includes an automatic rate detection system embodied in a second integrated circuit, where the first integrated circuit is in data communication with the second integrated circuit. Also, the automatic rate detection system is configured to determine a data rate of the data stream upon identifying a transition in the data rate of the data stream based upon the state of the at least one status flag received from the clock and data recovery circuit.

Automatic data rate detection

A method and apparatus for signal amplification and decision device operation on a signal which has a magnitude, peak value, or other average power that varies over time. In general, a peak detector detects the peak value of a received signal and responsive to the peak value, selectively enables a decision device when the signal is amplified to increase decision device accuracy. The decision may occur before the amplification forces the signal into saturation. Multi-stage amplification in combination with controlled switching or multiplexing may be utilized to selectively amplify the signal and selectively initiate decision device operation. The peak detector value may also control signal amplification levels in a multi-stage amplifier. Responsive to the peak value, a switch, which receives as its input the output from one or more amplifier stages, may be controlled to output the signal after a desired amount of amplification.

Multistage amplifier for rapid acquisition and random received signal power applications

Multiple ICs communicate with a controller through a shared bus. The ICs are also joined to an output of the controller in a daisy chain configuration. Each IC includes an input for receiving a signal on a link of the daisy chain and an output for providing a signal on a link of the daisy chain. The daisy chain links are used for address initialization. Thus only one controller pin and two IC pins are required for address initialization. The daisy chain links may be used for distributing address data, or may be used for distributing an enable signal that allows an IC to store address data provided on the shared bus.

Apparatus and methods for initializing integrated circuit addresses

A multiple channel signal processing circuit receives an input associated with a first channel and an input associated with a second channel. The respective inputs are sampled and processed by the circuit, which generates a sampled output signal for the first channel and a sampled output signal for the second channel. The circuit employs a shared active circuit component, such as an operational amplifier, to alternately process samples associated with the first and second channels. A network of switches are controlled by a multiphase clock signal such that the active circuit component processes samples associated with only one channel at a time; as the input for a first channel is being sampled, a previous sample for the second channel is processed. An alternate circuit embodiment may be utilized to reduce the amount of crosstalk between the channels.

Method and apparatus for multiple channel signal processing

Various exemplary aspects of the present invention provide methods and apparatus for powering down the line driver to a state that reduces power dissipation without affecting the overall impedance of the line driver. More particularly, a power down state for line drivers and the like is suitably provided that saves power when no transmission is required. The power down mode suitably provides line termination for received data. According to various aspects of an exemplary embodiment, output devices are configured at power down such that a low impedance is maintained.

Growing community of inventors

Newport Beach, CA, United States of America

Wim F Cops