Katholieke Universiteit Leuven

Infineon Technologies Ag

Imec Vzw

Imec

Stichting Imec Nederland

Other

Nxp B.v.

Semiconductor Components Industries, LLC

Stmicroelectronics N.v.

Hammer-Ims

Wim Dehaene

Andreas Wiesbauer

Jorg Daniels

Francky Catthoor

Stefan Cosemans

Vibhu Sharma

Kris Myny

Jos Huisken

Maryam Ashouei

Dietmar Straeussnigg

Marc Marcel Heyns

Anne S Verhulst

Luis Hernandez

Jan Genoe

Rita Rooyackers

Cedric Huyghebaert

Pieter Weckx

Mohit Gupta

Sushil Sakhare

Michiel Steyaert

Yves Vanderperren

Bharani Chakravarthy Chava

Daniele Leonelli

Florian De Roose

Jonas Pelgrims

Roel Lieve P Uytterhoeven

Noël Deferm

Junfeng Zhou

Peter Geens

Patrick Reynaert

Tom Redant

Lynn Verschueren

An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.

Timing error detection and correction circuit

A method of generating ultrasound by driving an array of ultrasonic transducers comprises a charge transfer procedure. The charge transfer procedure comprises switching a terminal of a first ultrasonic transducer of the array, at a first electric potential, to a charge distribution bus; switching a terminal of a second ultrasonic transducer of the array, at a second electric potential different than the first potential, to the charge distribution bus; and allowing charge to flow between the first ultrasonic transducer and the second ultrasonic transducer through the charge distribution bus.

Method of generating ultrasound and ultrasound generator

A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

Multibit neural network

A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.

Active matrix display and method for driving an active matrix display

The present invention relates to a millimeter or terahertz wave sensor for providing inline inspection, preferably including but not limited to continuous monitoring of objects, for example thin sheet dielectric material.

Sensor for non-destructive characterization of objects

A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

Local write and read assist circuitry for memory device

A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

Variability resilient sense amplifier with reduced energy consumption

This disclosure relates to analog to digital conversion using irregular sampling. A method may include combining an analog signal with a feedback signal into a combined signal, filtering the combined signal using a digital noise shaping filter into a combined noise shaped signal, modulating the combined noise shaped signal into a modulated signal, generating samples of the modulated signal, and reconstructing as a digital signal the analog signal from the samples of the modulated signal.

Asynchronous sigma delta analog to digital converter using a time to digital converter

An apparatus is provided which has a first analog input and a second analog input. In a particular implementation, the first analog input is coupled to a first controllable oscillator and the second analog input is coupled to a second controllable oscillator. First and second digital output signals generated based on output oscillations from the first controllable oscillator and the second controllable oscillator are combined.

Analog-to-digital converter using oscillators

This disclosure relates to analog to digital conversion using irregular sampling.

Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix.

Memory device with reduced standby power consumption and method for operating same

A regulator circuit receives a power supply and provides a regulated power supply output suitable for integrated circuitry. It has a controllable current source circuit, a controller and a capacitor, such that an output of the controllable current source circuit can provide a lower frequency current part of the regulated power supply output, and the capacitor can supply a higher frequency current part of the regulated power supply output. The controllable current source circuit is controlled according to feedback from the regulated power supply output, and to restrict a rate of change of the output of the controllable current source circuit. The amount of EMI noise caused by high rate of change of current in power supply lines to the regulator circuit can be reduced. This can be done more efficiently or using a smaller capacitor than known arrangements.

EMI suppressing regulator

A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is disclosed.

Multiple output time-to-digital converter

A receiver and a method for receiving a signal including a carrier modulated with a known training sequence is described in which an estimate a carrier frequency offset is obtained from an autocorrelation signal by autocorrelation of the part of the received signal containing a known training sequence. The received signal is compensated with the frequency offset obtained to form a compensated received signal, and a timing reference for the received signal is obtained by cross-correlation of the compensated received signal with a known training sequence.

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Kessel-lo, Belgium

Wim Dehaene