Altera Corporation

Wilson Wong

Sergey Yuryevich Shumarayev

Tim Tri Hoang

Rakesh H Patel

Thungoc M Tran

Weiqi Ding

Allen K Chan

Simardeep Maangat

Tin H Lai

John E Turner

Kazi Asaduzzaman

Chong H Lee

Mei Luo

Thomas Henry White

John D Lam

Bill W Bereza

Ali Atesoglu

Richard G Cliff

Shuxian Chen

William W Bereza

Albert Ratnakumar

Jie Shen

Wei Li

Sriram Narayan

Xiong Liu

Mengchi Liu

Xiaoyan Su

Doris Po Ching Chan

Sharat Babu Ippili

Qi Xiang

Jeffrey T Watt

Peng T Li

In Whan Kim

Kevin A Norman

Jun Liu

Arch Zaliznyak

Christopher J Pass

Fangyun Richter

Mingde Pan

Yanjing Ke

Che Ta Hsu

Jeffrey Xiaoqi Tung

Xudong Shi

Sangeeta Raman

Vishal Giridharan

Deepa Ratakonda

John Dung-Ngoc Lam

Mengchi Lui

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

High-speed serial data signal receiver circuitry

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g.,parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.

Multimode current mirror circuitry

A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.

Pre-emphasis circuitry including a pre-emphasis voltage variation compensation engine

A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.

Shielded metal-oxide-metal (MOM) capacitor structure

A method of equalizing an input data signal using a multiple-stage continuous-time linear equalization (CTLE) circuit. A zero-forcing least-mean-square (ZF LMS) procedure is applied to adapt the settings of the CTLE stages. The amplitude settings and the frequency boost settings of the CTLE stages are adapted within the ZF LMS procedure. In an exemplary implementation, an error screening threshold may be applied to an error signal within the ZF LMS procedure to generate a reduced error signal such that weight updates do not occur if the error signal is below the error screening threshold. In addition, if an accumulated sign error signal within the ZF LMS procedure reaches a predetermined maximum indicative of a high loss channel, then a setting for a variable gain amplifier may be increased, and an amplitude setting for the CTLE circuit may be decreased. Other embodiments, aspects and features are also disclosed.

Methods and apparatus for multiple-stage CTLE adaptation

The present disclosure provides a floating-tap decision feedback equalization (DFE) circuit. In an exemplary implementation, the floating-tap DFE circuit may include a high-speed shift register, a deserializer and data selector, a bypass deserializer, a high-speed multiplexer and a tap generation circuit. In one aspect of the invention, the floating-tap DFE circuit may advantageously cover an entire tap range beyond a fixed tap range without holes over a range of data rates. Other embodiments, aspects and features are also disclosed.

Floating-tap decision feedback equalizer

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates&#x2014;e.g., 1 Gbps&#x2014;circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates&#x2014;e.g., 3 Gbps&#x2014;modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates&#x2014;e.g., 6 Gbps&#x2014;more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates&#x2014;e.g., 10 Gbps&#x2014;on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

Power supply filtering for programmable logic device having heterogeneous serial interface architecture

A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

High resolution capacitor

An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.

Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimization

An integrated circuit is presented. The integrated circuit includes a selection circuit that selects a reference voltage and an output voltage associated with a number of adjustable voltage regulators connected to the selection circuit. The integrated circuit also has an analog to digital converter, which converts the selected output voltage and the reference voltage to a digital representation. An analog state machine of the integrated circuit receives the digital representation from the analog to digital converter and compares the selected output voltage with the reference voltage.

Adjustable voltage regulator calibration circuit

Disclosed are apparatus and methods to advantageously calibrate a transmitter output swing. One embodiment relates to a method for calibrating the output swing voltage of a transmitter. A fixed value is provided as the data input, and output swing calibration circuitry is connected to the transmitter buffer circuit. A transmitter current is set to an initial level, and the transmitter current is adjusted until the output swing of the transmitter buffer circuit is calibrated. Another embodiment relates to an integrated circuit which includes a transmitter buffer circuit, output swing calibration circuitry, and switches arranged to electrically connect the transmitter buffer circuit to the output swing calibration circuitry during an output swing calibration mode. Another embodiment relates to an output swing calibration circuit which includes comparison circuitry and logic and control circuitry.

Apparatus and methods for transmitter output swing calibration

A phase-locked loop circuit includes an oscillator circuit that generates a clock signal. The oscillator circuit has gears. Each of the gears of the oscillator circuit corresponds to a respective frequency range of the clock signal. A gear control circuit includes a regulator circuit that provides a supply voltage to the oscillator circuit. Each of the gears of the oscillator circuit corresponds to a different supply voltage provided by the regulator circuit. The regulator circuit varies the supply voltage to change a selected one of the gears of the oscillator circuit. The gear control circuit varies the supply voltage for one of the gears of the oscillator circuit to adjust a frequency range of that gear of the oscillator circuit.

Techniques for adjusting gears of an oscillator

Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Integrated circuits with configurable inductors

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San Francisco, CA, United States of America

Wilson Wong