Xilinx, Inc.

Silicon Storage Technology, Inc.

Brocade Communications Systems, Inc.

Triscend Corporation

Wilson Kaming Yee

Danesh Tavana

Stephen M Trimberger

Victor A Holen

Steven P Young

David P Schultz

Joseph I Chamdani

Sridhar Krishnamurthy

Richard D Reohr, Jr

Bart Reynolds

Fung Fung Lee

Scott O Frake

Brian Fox

Jane W Sowards

Edmond Y Cheung

Steven Winegarden

Tsung-Lu Syu

Litko Chan

James L McManus

A programmable integrated circuit has a plurality of logic elements with each logic element having a plurality of input leads and at least one output lead. The programmable integrated circuit further comprises a group of interconnect lines, and a first set of programmable circuits for electrically connecting the input and output leads of the plurality of logic elements to each other through the group of interconnect lines. The programmable integrated circuit further comprises a test circuit having at least one input and one output. Further the programmable integrated circuit comprises a second set of programmable circuits for electrically connecting the one output of the test circuit to the plurality of input leads of each of the plurality of logic elements and for electrically connecting the at least one output lead of each of the plurality of logic elements to the one input of the test circuit, through the group of interconnect lines.

Programmable integrated circuit having built in test circuit

Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A storage resource identifier corresponding to the target identifier is determined according to a forwarding table. A sequence identifier is associated with the source identifier, where the sequence identifier corresponds to the target. The source identifier and the sequence identifier are recorded at a context table, and the data packet is routed according to the storage resource identifier.

Processing data packets at a storage service module of a switch

Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.

Programmable interface for a configurable system bus

An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and the output buffer of the PLD are disabled. In one embodiment, a predetermined voltage is provided on the output terminal of the input buffer. In this configuration, the hot swap circuit eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD.

Method and system for PLD swapping

A method and system for the rapid and precise configuration of a bank of logic in a configurable system on a chip. The configuration memory array is partitioned into a plurality banks. Configuration circuitry is implemented for each bank. This allows for the configuration of one or more banks while the other banks remain operable.

Bank-based configuration and reconfiguration for programmable logic in a system on a chip

The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths are implemented in dedicated logic while other portions of the clock enable circuit are implemented using programmable logic. According to another embodiment of the invention, the clock enable circuit is located near the center of a first edge of the device. A first plurality of output registers are located along the first edge on either side of the clock enable circuit, with additional output registers being located along the two adjacent half-edges. Programmable interconnection points (PIPs) permit a clock enable interconnect line along the first edge to be programmably extended to the additional output registers. In another embodiment, the clock enable circuit is duplicated in two opposite edges of the device.

Structure and method for generating a clock enable signal in a PLD

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Integrated circuit with field programmable and application specific

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.

FPGA architecture with repeatable titles including routing matrices and

FPGA architecture with repeatable tiles including routing matrices and

A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other of the inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.

Programmable scan chain testing structure and method

A circuit and method in a field programmable gate array (FPGA) for eliminating programming contentions which occur during array configuration comprises a switching matrix of crossing lines, in which cross points, called programmable interconnection points (PIPs), are connected by configuration transistors. The configuration transistors can be programmed to connect the lines at the PIPs or to leave the lines unconnected. Output drivers are selectively connected by the PIPs to the signal lines. Prior to the configuration and reconfiguration of the FPGA, drivers to the gate array are disabled to prevent potentially catastrophic driver contention. The contention eliminating circuit of the present invention holds the logical values of the output buffers to a single logic level until programming has been completed. The circuit of the preferred embodiment comprises a two input AND gate which combines the incoming data signals with a gating signal. The first set of AND gate inputs receives and transmits the incoming data used for driving the input buffers. The second set of inputs to the AND gates receives enable signals which control the propagation of the input data to the PIP array until programming of the PIPs is completed.

Growing community of inventors

Pleasanton, CA, United States of America

Wilson Kaming Yee