Xilinx, Inc.

Cisco Technology, Inc.

Wilson Chung

Gabor Szedo

Toader-Adrian Chirila-Rus

Robert D Turney

Ali C Begen

Wael Badawy

Peter Szántó

Béla Fehér

Ihab Amer

Plural representations of a video stream may be provided. The plural representations may comprise a first chunk, a second chunk, and a transition chunk. The first chunk may comprise a first bitrate and the second chunk may comprise a second bitrate. The first and second chunks may be in decode order starting with an instantaneous decoding refresh (IDR) frame. The transition chunk may be in decode order starting with a non-IDR frame. Next, a request to transition from the first chunk to the second chunk may be received. Then a transition from the first chunk to the transition chunk responsive to the request may occur and the transition chunk may then be provided to another device.

Bandwidth-friendly representation switching in adaptive streaming

A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.

Scalable architecture for rank order filtering

A method and apparatus for an adaptive systolic array structure is initially configured for motion estimation calculations and optionally reconfigured as the motion estimation algorithm progresses. A scheduling map of the processing element (PE) calculations for a given motion estimation algorithm is generated. A systolic array structure may then be generated from the scheduling map, whereby the size and shape of a processing element array is configured to generate the search pattern that is to be used during the search. In addition, delay elements may be implemented within the systolic array structure, so as to preserve the pixels of a current macroblock that are reused in accordance with the scheduling map. The systolic array structure may also be adapted by the motion estimation algorithm during subsequent search stages to accommodate refinements required by the search strategy.

Method and apparatus for an adaptive systolic array structure

A data structure and method of use thereof for encoding video information are described. Macroblock parameters are initialized, and it is determined whether an operating point is selected. If the operating point is selected, then the following occurs: each quad of nodes of a first node level are obtained and a check for merger is done on them; each quad of nodes of a second node level is obtained and a check for merger is done on them; nodes of a third node level are obtained and check for merger is done on them; nodes of a fourth node level are obtained and a check for merger is done on them; and modes are assigned responsive to cost of combinations of encoding modes associated with possible mergers.

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Menlo Park, CA, United States of America

Wilson Chung