Taiwan Semiconductor Manufacturing Comp. Ltd.

Intel Corporation

Micron Technology Incorporated

University of California

Leland Stanford Junior University

Wilman Tsai

Prashant Majhi

Jack T Kavalieros

Ling-Yen Yeh

Shy-Jay Lin

Chih-Sheng Chang

Chi On Chui

Carlos H Diaz

Mingyuan Song

Chien-Hsing Lee

Chia-Wen Chang

Yee-Chia Yeo

Cheng-Hsien Wu

Stefan Rusu

I-Sheng Chen

Niti Goel

Kyu S Min

Ming-Yuan Song

Hong-Nien Lin

Jeff N Farnsworth

Gilbert W Dewey

Yu-Ming Lin

Marko Radosavljevic

Willy Rachmady

Niloy Mukherjee

Jun-Fei Zheng

George K Chen

Yong Ju Lee

Frederick Chen

Marilyn Kamna

Ravi Pillarisetty

Ian A Young

Benjamin Chu-Kung

Andrew C Kummel

Zi-Wei Fang

Hsiang-Pi Chang

Qi-De Qian

Paul A Zimmerman

Paul C McIntyre

Yoshihiro Tezuka

Kasra Sardashti

Fred T Chen

Iljo Kwak

Hong-Fa Luan

Scott Ueda

Mahmut Kavrik

Steven Labovitz

Balreen Saini

John D Baniecki

Zhouchangwan Yu

Maximillian Clemons

Niti Goe

Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

MRAM stacks, MRAM devices and methods of forming the same

Ferroelectric materials and more particularly cerium-doped ferroelectric materials and related devices and methods are disclosed. Aspects of the present disclosure relate to ferroelectric layers of hafnium-zirconium-oxide (HZO) doped with cerium that enable reliable ferroelectric fabrication processes and related structures with significantly improved cycling endurance performance. Such doping in ferroelectric layers also provides the capability to modulate polarization to achieve a desired operation voltage range. Doping concentrations of cerium in HZO films are disclosed with ranges that provide a stabilized polar orthorhombic phase in resulting films, thereby promoting ferroelectric capabilities. Exemplary fabrication techniques for doping cerium in HZO films as well as exemplary device structures including metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) structures are also disclosed.

Cerium-doped ferroelectric materials and related devices and methods

In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.

Method of manufacturing semiconductor device including ferroelectric layer having nano crystals

A device includes a spin orbit coupling layer and a Magnetic Tunnel Junction (MTJ) stack. The MTJ stack includes a dielectric layer over the spin orbit coupling layer, a free layer over the dielectric layer, a tunnel barrier layer over the free laver, and a reference layer over the tunnel barrier layer. The spin orbit coupling layer extends beyond edges of the MTJ stack in a first direction and a second direction opposite to the first direction.

SOT MRAM having dielectric interfacial layer and method forming same

A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.

Magnetic device and magnetic random access memory

MRAM stacks and memory devices

Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.

Method for forming semiconductor device structure with nanowires

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Semiconductor device and manufacturing method thereof

A method includes depositing a plurality of layers, which includes depositing a spin orbit coupling layer, depositing a dielectric layer over the spin orbit coupling layer, depositing a free layer over the dielectric layer, depositing a tunnel barrier layer over the free layer, and depositing a reference layer over the tunnel barrier layer. The method further includes performing a first patterning process to pattern the plurality of layers, and performing a second patterning process to pattern the reference layer, the tunnel barrier layer, the free layer, and the dielectric layer. The second patterning process stops on a top surface of the spin orbit coupling layer.

In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam.

Method of manufacturing semiconductor devices

Semiconductor device with negative capacitance comprising ferroelectric layer including amorphous and crystals

A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.

Semiconductor device including standard cells with header/footer switch including negative capacitance

Method of manufacturing semiconductor device including ferroelectric layer having columnar-shaped crystals

Growing community of inventors

Saratoga, CA, United States of America

Wilman Tsai