International Business Machines Corporation

Wilm Ernst Donath

David James Hathaway

Dennis Merton Newns

Prabhakar Nandavar Kudva

Mark Alan Lavin

Pratap Chandra Pattnaik

Paul Gerard Villarrubia

Gustavo Enrique Tellez

Lakshmi Narasimha Reddy

Jerome M Kurtzberg

Wing Kin Luk

Daniel Nelson Maynard

Jeffrey Paul Soreff

Donald T Tang

Leon Stok

Andrew James Sullivan

Helmut Roth

Archibald John Allen

Stephen E Bello

Kanad Chakraborty

Alan Dziedzic

Cyril A Price

Robert B Hitchcock

Robert B Hitchcock, Sr

Roger I McMillan

Joseph Hutt, Jr

San Y Han

Bhuwan Agrawal

Reini J Norman

Ralph W Wilk

A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.

Method and apparatus for applying fine-grained transforms during placement synthesis interaction

A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

Method for prediction random defect yields of integrated circuits with accuracy and computation time controls

A method of distributed timing analysis for a network which has been partitioned into at least two partitions, with each partition being assigned to a separate timing analysis process which communicates with the other processes is provided. A depth first search is performed by the process assigned to the partition in which the node for which timing information is desired is located. When the depth first search encounters a node for which a timing value is required which is located in another partition, a request is immediately sent to the process corresponding to that partition for the required timing information. When the request for timing information from the other partition is answered, the associated node is placed in the propagation queue. Also, as a node is processed, successor nodes which have had their predecessors processed are added to the propagation queue. The nodes in the propagation queue are processed and timing values are computed. When there are no nodes in the propagation queue, global loop detection is performed. Additionally, incremental timing updates are performed when a change is made in the network.

Distributed static timing analysis

The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve these nets or paths. Once sets of motions have been generated, they are tested to determine the most beneficial movement for improving the given circuit parameter (e.g., wireability, timing, etc.).

Method for improving the assignment of circuit locations during fabrication

A method and structure for a field effect transistor (FET) includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate region, and a gate oxide region separating the gate region from other regions of the FET. The channel region is a Mott insulator. The gate oxide region is thicker than the channel region, and the gate oxide region includes a higher dielectric permittivity than the Mott insulator material.

Ultrafast nanoscale field effect transistor

A method of distributed timing analysis for a network which has been partitioned into at least two partitions, with each partition being assigned to a separate timing analysis process which communicates with the other processes is provided. A depth first search is performed by the process assigned to the partition in which the node for which timing information is desired is located. When the depth first search encounters a node for which a timing value is required which is located in another partition, a request is immediately sent to the process corresponding to that partition for the required timing information. When the request for timing information from the other partition is answered, the associated node is placed in the propagation queue. Also, as a node is processed, successor nodes which have had their predecessors processed are added to the propagation queue. The nodes in the propagation queue are processes and timing values are computed. When there are no nodes in the propagation queue, global loop detection is performed. Additionally, incremental timing updates are performed when a change is made in the network.

A method of speeding up computer simulation/emulation of circuit logic designs. The method converts an original circuit logic design (intended for hardware packaging) to a different circuit form before starting computer simulation/emulation. The converted circuit form provides the same simulation/emulation results as would have been obtained with the original logic circuit. The method operates with multi-phase logic designs comprised of gate circuits using multi-phase clocking of the type commonly packaged in semiconductor chips. The method converts such multi-phase logic designs into a single-phase circuit form, which is presented to the computer for simulation/emulation that provides the same results as the multi-phase logic design but at a much faster speed. The method is presented with a multi-phase logic design containing flip-flops as the internal storage circuits. The method effectively retains the storage circuits found in a multi-phase logic design and replicates its logic blocks providing multiple phase outputs. Then the storage circuits are reconnected to the original and replicated logic blocks in a manner that enables a single clock cycle to operate the converted logic design to simulate/emulate the same results in the storage circuits, as if the original multi-phase logic design were being simulated or emulated, but at a much faster speed.

Logic translation method for increasing simulation emulation efficiency

A method and apparatus for minimizing the total power of a logic network subject to timing constraints. The method describes a procedure to assign power and/or delay to each circuit in a logic network such that the total power is minimized and the arrival time requirement at the outputs of the logic network is met. A subset of circuits in the logic network are powered up and powered down in repeated succession in order to minimize the total power of the logic network.

Procedure to minimize total power of a logic network subject to timing

An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory). Other enhancements include application enhancements by providing generality of methodology and accommodation of large model size, further computational enhancement by providing generality of delay propagation algorithms and diagnostic enhancements by providing cycle time/yield data and allowance of re-simulation of failure modes of design performance by retaining seed values corresponding to simulated machines.

Method for evaluating the timing of digital machines with statistical

The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.

Timing driven placement

A method is provided which is applied to a logic block diagram, referred to as a block graph, which consists of a plurality of logic blocks interconnected by nets which carry logic signals between the logic blocks. The method is used to determine the characteristics of the given block graph, and more particularly to analyze the block graph to identify critical paths wherein logic signals must arrive at designated blocks at a critical time, and to determine whether the path delays of such critical paths are too long or too short. When critical paths are identified which have path delays that are too long or too short, the block graph can be redesigned to avoid such delays. The method includes three basic, broad steps each of which incorporates a plurality of subsidiary implementation steps. First, from the logic block graph, special blocks defined as storage elements because of their unique function are identified and classified as 'level zero' elements. Second, a procedure is carried out which 'levelizes' the remaining blocks in the block graph, that is, the blocks will be designated level two, level three, level four etc. in accordance with rules defined within the method. Finally, the long and short path delays, referred to as the extreme characteristics and identified by extreme values are determined for each block in level one, followed by a determination of the extreme characteristics of each block in level two, level three, etc. The extreme characteristics thus identify the critical paths within the logic block which are too long or too short so that a redesign can be made.

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New York, NY, United States of America

Wilm Ernst Donath