Spansion Llc.

Cypress Semiconductor Corporation

Willy Obereiner

Jeremy Isaac Nathaniel Werner

Venkat Natarajan

Joe Yuen Tom

Mark Alan McClain

Russell Barck

Rainer Hoehler

Hyun Soo Lee

George Minassian

Hendrik Graulus

In an example embodiment, a device comprises a non-volatile memory and wear leveling control circuitry. The non-volatile memory comprises logical memory sectors mapped to physical memory sectors, and a supervisory memory sector configured to store a mapping of the logical memory sectors to memory partitions with user-defined boundaries. The wear leveling control circuitry is configured to: receive and store, in the mapping, wear leveling parameters based on user input, where each memory partition is associated with a wear leveling parameter indicating whether that memory partition is excluded from wear leveling; and determine and apply, to the non-volatile memory, wear leveling characteristics based on the wear leveling parameters, where the wear leveling characteristics identify an amount of wear leveling allowed for each of the memory partitions.

Systems, methods, and devices for user configurable wear leveling of non-volatile memory

Disclosed herein are systems, methods, and devices for user configurable wear leveling of non-volatile memory devices. Devices include a non-volatile memory including a plurality of physical memory portions, where each of the plurality of physical memory portions is configured to be mapped to a logical memory portion of a plurality of logical memory portions. Devices may also include wear leveling control circuitry configured to receive a plurality of wear leveling parameters, and further configured to determine a plurality of wear leveling characteristics based on the plurality of wear leveling parameters received, where the plurality of wear leveling characteristics identify an amount of wear leveling allowed for each of the plurality of logical memory portions.

An architecture is presented that facilitates integrated security capabilities. A memory module is provided that comprises non-volatile memory that stores security software and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. Further, a host processor located outside of the memory module arbitrates with the security processor for access to the non-volatile memory. The memory module in communication with the host processor establishes a heightened level of security that can be utilized in authentication services and secure channel communications.

Secure co-processing memory controller integrated into an embedded memory subsystem

A machine implemented system and method that effectuates secure access to a flash memory associated with a mobile device. The system includes a security component that intercepts transactions between an external processor and the flash memory and implements authentication and access control to the flash memory. The system further includes components that can partition the flash memory and can associate authentication and access control information with the partitioned flash memory.

Multiple stakeholder secure memory partitioning and access control

An architecture is presented that facilitates maintaining a log of near field transactions in a memory module that includes security functionalities and near field communication (NFC) capabilities. The memory module comprises non-volatile memory that stores security software and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. The non-volatile memory is divided into partitions by the security processor. NFC radio frequency (RF) communication capabilities are integrated into the memory module such that the memory module directly interfaces to an external NFC antenna. This facilitates NFC communications within the secure environment of the memory module. Further, the memory module stores data related to near field transactions so that this data can be subsequently reviewed and exported in an appropriate format.

Non-volatile memory sub-system integrated with security for storing near field transactions

Systems and/or methods that facilitate controlling access to memory regions in a memory component(s) are presented. A memory component can comprise an access management component that can facilitate controlling access to memory regions that can be respectively associated with authentication credentials. The access control component can facilitate access of a memory region when received authentication information matches authentication information contained in a security record associated with the memory region. The access management component can facilitate a wipe erase of a memory region(s) to facilitate secure removal of information from the memory region when predetermined criteria is satisfied. The access management component can facilitate locking a memory region when a maximum number of attempts to access a memory region are unsuccessful to facilitate security of the memory regions and/or data associated therewith, where a locked memory region remains locked until a reset is performed.

Secure management of memory regions in a memory

Systems and methods that facilitate processing data, such as by encryption/decryption, and storing and retrieving data to/from memory such that actual data can be distinguished from information associated with, or representative of, erased/blank memory locations. A processor can include a comparing component that compares information input to the processor to determine whether such information is associated with actual data, or associated with, or representative of, erased/blank memory locations. Information associated with, or representative of, an erased/blank memory location can be processed so that it can be interpreted as such by other components. If actual data is processed such that the comparing component interprets the processed data to be equivalent to an erased/blank memory location, then the data can be re-processed, so it is not interpreted as such, before being forwarded to its next destination.

Systems and methods for distinguishing between actual data and erased/blank memory with regard to encrypted data

Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an idle state. The host memory interface can analyze authentication information obtained via an authentication component, and information regarding memory partition rights, to determine whether a command partition violation exists as to the command. If a violation exists, the host memory interface can prevent the improper command from executing in the memory, and can cause a different operation to occur thereby allowing the memory to be placed in a known state.

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San Jose, CA, United States of America

Willy Obereiner