International Business Machines Corporation

Infineon Technologies North America Corp.

William Wu Shen

Chin-Long Chen

Mu-Yue Hsiao

Patrick James Meaney

Walter Heinrich Lipponer

Russell W Lavallee

Kevin W Kark

Matthew A Krygowski

George C Wellwood

Giacomo Vincent Ingenio

Charles D Holtz

Louis L Hsu

Paul William Coteus

Toshiaki Kirihata

William Paul Hovis

Pak-kin Mak

Li-Kong Wang

Brian William Curran

Thomas M Brey

Tin-Chee Lo

Gary E Strait

Trinh Huy Nguyen

Sanjay Bhikhubhai Patel

Charles F Pells

Udo Wille

Henry Chin

Arthur J Sutton

Bruce L McGilvray

Hartmut Ulland

Kenneth Y Chan

Donald G O'Brien

Frank P Cartman

Vesselina K Zaharinova-Papazova

Sandy N Luu

Surasak K O'Trakoun

Klaus Ruediger Baat

Michael Rubino

The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Address wrap function for addressable memory devices

Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

Multi-cycle symbol level error correction and memory system

The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.

High speed embedded DRAM with SRAM-like interface

A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a lesser number of banks. To accomplish this, a control (bit) is produced on the chip Mode Register Set (MRS) that activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip so that a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and that has a format of a lesser number of bank ID bits.

Multi-bank chip compatible with a controller designed for a lesser number of banks and method of operating

Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

Power governor for dynamic RAM

Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.

Generating special uncorrectable error codes for failure isolation

In a computer RAM memory system, the memory is subjected to a self test operation during which data is written to and read out from each address location of the memory. The data read out is compared with the written data to detect errors and the number of errors at each bit position is counted. When the number of errors in a bit position-exceeds a selected threshold, the corresponding DRAM is replaced by a spare DRAM. When the self test detects two or more errors in the same double word, the DRAM corresponding to the bit position having the highest error count is replaced with a spare DRAM. The memory is periodically scrubbed and errors detected during the scrubbing operation are counted for each bit position. At the end of the scrubbing of a chip row the DRAMs corresponding to bit positions at which the error counts exceed a selected threshold are replaced with spare DRAMs. When a multiple bit error in a double word is detected during scrubbing, the corresponding double word is tagged.

Computer RAM memory system with enhanced scrubbing and sparing

An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.

Single symbol correction double symbol detection code employing a modular H-matrix

Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.

Method system and program products for error correction code conversion

Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.

Detecting address faults in an ECC-protected memory

In a memory card, identification numbers identifying the memory card are permanently stored in fuse blown registers formed in each of two redrive chips, which function to read out data from memory chips of the memory card and store data in the memory chips of the memory card. Each identification number separately provides a unique identification of the memory card. The identification numbers are each stored with an error correction code by which single bit errors en the identification numbers can be corrected and the occurrence of multiple bit errors in the identification numbers can be detected. Both identification numbers, if valid, are used to identify the memory card and both of the identification numbers, if valid, are stored in association with memory quality events occurring on the memory card, so as to provide a redundant identification of the memory card on which the memory quality events occurred.

Memory card identification system

A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

Memory card interface method using multiplexed storage protect key to indicate command acceptance

A computer system having central processors (CPs), an associated L2 cache, and processor memory arrays (PMAs), is provided with store logic and and fetch logic used to detect and correct data errors and to write the resulting data the associated cache. The store logic and and fetch logic blocks UEs from the cache for CP stores, for PMA (mainstore) fetches/loads, and for cache-to-cache loads, and with uncorrectable error recovery cache fetch and store logic injects `Special UEs` into the cache when loads cannot be blocked and abends CP jobs for UEs during CP stores, for UEs from PMA, for UEs from remote cache, and for UEs from local cache. This logic performs reconfiguring of memory when UEs are detected in memory and also blocks cache data propagation on UEs for CP fetches, for Cache-to-Cache transfer if data is unchanged, and for PMA castouts if data is unchanged, as well as forces castouts when UEs appear on changed cache data; injects `Special UEs` for UEs detected on changed cache data; invalidates the cache when UEs are detected in the local cache; and only deletes cache entries that have repeated failures.

Computer system UE recovery logic

A memory request protocol allows a memory request to be withdrawn or 'cancelled' without penalty so no memory resource is wasted in doing so during an assigned 'cancel window'. When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or 'cancel window'.

Memory request protocol method

A memory control device, having a common synchronous interface coupled thereto, for accessing asynchronous memory devices, as well as other synchronous devices. The memory control device receives, via the synchronous interface, a command having a synchronous format, and translates at least a portion of the command from the synchronous format to an asynchronous format. The command in the asynchronous format is then used to access an asynchronous memory device. The asynchronous memory device can have one of various formats, each of which is supported by the memory control device. The memory control device emulates synchronous memory devices for the system memory controller coupled to the memory control device, even when asynchronous devices are accessed. The memory control device can also translate commands from one synchronous format to another synchronous format such that memory devices of the another synchronous format can be accessed.

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Poughkeepsie, NY, United States of America

William Wu Shen