Taiwan Semiconductor Manufacturing Comp. Ltd.

William Wu Shen

Lan-Chou Cho

Huan-Neng Chen

Chewn-Pu Jou

Feng Wei Kuo

Yun-Han Lee

Chin-Chou Liu

Hsien-Hsin Sean Lee

Feng-Wei Kuo

Chin-Her Chien

Bo-Jr Huang

Jack Liu

Tze-Chiang Huang

Wen-Shiang Liao

Wei-Cheng Wu

Ching-Fang Chen

Chao-Yang Yeh

Chung-Sheng Yuan

Jiun Yi Wu

Fu-Lung Hsueh

Po-Hsiang Huang

Chung-Min Fu

Chi-Yeh Yu

Meng-Fu You

Chien Hsun Lee

Chien Hsun Chen

An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Integrated circuit with radio frequency interconnect

A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

Memory circuit and cache circuit configuration

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits

The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.

Integrated antenna on interposer substrate

A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.

An integrated circuit includes a first through fourth devices positioned over a substrate, the first device including first through third transceivers, the second device including a fourth transceiver, the third device including a fifth transceiver, and the fourth device including a sixth transceiver. A first radio frequency interconnect (RFI) includes the first transceiver coupled to the fourth transceiver through a first guided transmission medium, a second RFI includes the second transceiver coupled to the fifth transceiver through a second guided transmission medium, and a third RFI includes the third transceiver coupled to the sixth transceiver by the second guided transmission medium.

A communication system includes a transmitter configured to transmit a modulated signal, a transmission line configured to carry the modulated signal, and a receiver coupled to the transmitter by the transmission line, and configured to receive the modulated signal. The transmitter includes a modulator configured to generate the modulated signal responsive to a data signal and a carrier signal. The receiver includes a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit configured to adjust a gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.

Communication system and method of data communications

A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.

Systems and methods for die-to-die communication

A circuit includes a transmitter, a transmission channel communicatively coupled with the transmitter, and a receiver communicatively coupled with the transmission channel. The circuit further includes a combiner on a transmitter-side of the transmission channel, a decoupler on a receiver-side of the transmission channel, and a channel loss compensation circuit communicatively coupled between the transmitter and the receiver. The combiner is coupled between the transmitter and the transmission channel. The decoupler is coupled between the receiver and the transmission channel.

Channel loss compensation circuits

A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.

The present disclosure relates to an integrated antenna structure. The integrated antenna structure includes a radiator and a ground plane disposed between a semiconductor substrate and the radiator. A conductive structure is separated from the ground plane by the semiconductor substrate. The conductive structure is electrically coupled to the ground plane. The semiconductor substrate has a thickness of less than approximately 100 microns.

A communication system includes a modulator configured to generate a modulated signal responsive to at least a data signal, and a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter configured to generate a filtered first signal based on a first signal, and a gain adjusting circuit coupled to the filter. The first signal is based on the first carrier signal and modulated signal. The filter has a gain controlled by a set of control signals. The gain adjusting circuit is configured to adjust the gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.

Growing community of inventors

Hsinchu, Taiwan

William Wu Shen