Texas Instruments Corporation

William Wesley Dostalik

Robert Kraft

Ping Jiang

Yong Seok Choi

Lee M Loewenstein

Ting Yiu Tsui

Kenneth D Brennan

David Gerald Farber

Andrew McKerrow

Kenneth Joseph Newton

A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Poison-free and low ULK damage integration scheme for damascene interconnects

A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Method of passivating and/or removing contaminants on a low-k dielectric/copper surface

The present invention provides a method for etching a substrate. The method includes conducting a first etch through a dielectric layerlocated over an etch-stop layer, the dielectric layer having a photoresist layerlocated thereover and the first etch being selective to the etch-stop layer. A second etch different from the first etch is conducted on the etch-stop layer, the second etch including nitrogen and at least one fluorocarbon gas, such that the ratio of nitrogen to carbon in the etchant is greater than about 5:1.

Method for etch-stop layer etching during damascene dielectric etching with low polymerization

An embodiment of the invention is a dual damascene layerof an integrated circuitcontaining a dual damascene pattern liner. Another embodiment of the invention is a method of manufacturing dual damascene layerwhere a dual damascene pattern lineris formed over a cap layerand within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layerwhere a dual damascene pattern lineris formed over a cap layerand within trench spaces.

Dual damascene pattern liner

In one embodiment this is a method of clamping semiconductor wafers for processing with the active face down. The method comprises: supporting a face down wafer 10 on an intermediate support 15; placing a clamping surface 14 at least adjacent to a backside of the wafer; moving at least three bevel-edged pins 11 upward to engage the beveled edges 12 with portions of the periphery of the face to press the wafer 10 against the clamping surface 14; moving the intermediate support 15 away from the wafer 10, and removing photoresist from the wafer by ashing the photoresist, whereby photoresist is essentially completely removed and essentially no unremoved photoresist remains to contaminate later processing.

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Plano, TX, United States of America

William Wesley Dostalik