Hewlett-Packard Company

William Weiner

Kenneth Koch, Ii

Thomas N Indermaur

Matthew L Biggio

The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.

System and method for controlling delay times in floating-body CMOSFET inverters

A method and structure of power balancing is capable of simultaneously minimizing maximum power while also reducing the step load of any electronic system, subsystem, or device having one or more functional units or resources that are not in constant use and that are therefore capable of being selectively powered-down or powered-up.

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Windsor, CO, United States of America

William Weiner