Taiwan Semiconductor Manufacturing Comp. Ltd.

William Weilun Hong

Ying-Tsung Chen

Kei-Wei Chen

Che-Hao Tu

Po-Chin Nien

Chun-Wei Hsu

Liang-Guang Chen

Chih Hung Chen

Chi-Jen Liu

Chi-Hsiang Shen

Chia-Wei Ho

Yang-Chun Cheng

Yi-Sheng Lin

Cheng-Yu Kuo

Te-Ming Kung

Te-Chien Hou

Yu-Ting Yen

I-Shuo Liu

Chih-Chun Hsia

Kuanhua Su

Chih-Wen Liu

Hsin-Ting Chou

Wen-Chih Chiou

Syun-Ming Jang Jang

Chih-Yu Chang

Ying-Ho Chen

Shich-Chang Suen

Gin-Chen Huang

Chia-Che Chung

Ji Cui

Wan-Chun Pan

Kuo-Min Lin

Chi-Wei Chung

Gang Huang

Hsin Ting Chou

A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

CMP system and method of use

A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Hotspot avoidance method of manufacturing integrated circuits

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Metal heterojunction structure with capping metal layer

A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Hard mask removal method

A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.

Post-CMP cleaning composition for germanium-containing substrate

Hotspot avoidance method for manufacturing integrated circuits

A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.

Chemical mechanical planarization using nano-abrasive slurry

A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.

Vias with metal caps for underlying conductive lines

The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.

CMP slurry and CMP method

Growing community of inventors

Hsinchu, Taiwan

William Weilun Hong