Fujitsu Corporation

Other

International Business Machines Corporation

Vertex Semiconductor Corporation

William Warren Walker

Nikola Nedovic

Nestor Tzartzanis

Subodh M Reddy

Rajeev Murgai

H Anders Kristensson

Hirotaka Tamura

Samir Parikh

Magnus Olov Wiklund

Pradip Thachile

Vojin G Oklobd{haeck Over (z)}ija

Roy E Scheuerlein

Wendell P Noble

Yolin Lih

Laurence H Cooke

Scott McLeod

Alexander Tomkins

Hongyu Chen

Vojin G Oklobdzija

Sorin P Voinigescu

Volin G Oklobdzija

Brent W Miller

Ranjeez Murgai

A method may include obtaining gate-level circuit design data that describes a gate-level circuit design. The gate-level circuit design data may include one or more instances of each of multiple cells that each may be associated with a corresponding default cell static timing data and a corresponding default cell stress data. The method may include selecting one of the instances of one of the multiple cells, determining in-design stress data associated with the selected instance, and determining whether the in-design stress data is not within a tolerance of the default cell stress data. In response to the in-design stress data not being within the tolerance of the default cell stress data, the method may include generating in-design static timing data describing a timing performance for the selected instance and updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data.

Performing static timing analysis in the presence of instance-based systematic variations

A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

Clock multiplication and distribution

In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

System and method for clock network meta-synthesis

A system for signal generation may include a phase-locked-loop including a first oscillator. The system may also include a second oscillator. The first oscillator may be configured to generate a first signal based on a phase-locked-loop control signal generated by the phase-locked-loop. The second oscillator may be configured to generate a second signal based on the phase-locked-loop control signal such that a free-running frequency of the first signal is approximately equal to a free-running frequency of the second signal to obtain injection locking between the first oscillator and the second oscillator when energy from the first oscillator is coupled into the second oscillator.

Monolithic signal generation for injection locking

A digital duty-cycle correction circuit may include an adjustment unit that may be configured to adjust a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal and a sampling unit that may be configured to sample the adjusted oscillating signal. The circuit may also include a counting unit that may be configured to generate an indication of a number of samples of the adjusted oscillating signal that are at the low and high level and to adjust the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusting oscillating signal. The circuit may also include a comparing and filtering unit that may be configured to generate the adjust signal based on a comparison of the indication with a comparison count. The indication may be adjustable such that the oscillating signal's duty cycle is adjustable.

Digital duty cycle correction

A system for generating behavioral models for analog circuits may include a database that is configured to store a parameterized hardware description language model of an analog circuit and an analog circuit simulator template of the analog circuit. The system may also include an interface module configured to receive data for an instance of the analog circuit in a schematic format. The system may also include an analog circuit simulator configured to use the received data and the analog circuit simulator template to generate a value for a parameter of the parameterized hardware description language model of the analog circuit. The system may also include a model constructor configured to generate a behavioral hardware description language model of the instance of the analog circuit based on the parameterized hardware description language model of the analog circuit and the generated value.

Generating behavioral models for analog circuits

A system includes an array of comparators configured to convert an analog input to a digital output, a switch configured to adjust output bits of the digital output, and a control logic; the control logic is configured to initialize the switch and a direct-current source coupled to the analog input; the control logic is configured to increase the direct-current source in incremental steps of a minimal voltage value corresponding to the least significant bit of the digital output; and the control input is also configured to cause the switch to adjust one or more output bits of the digital output based at least in part on a value of the output bit corresponding to the current incremental step.

Crossbar switch calibration system for facilitating analog-to-digital conversion monotonicity

In one embodiment, a circuit comprises a first pair of elements, a second pair of elements, a combiner, and a signal output. Each element in the first and second pair of elements comprises an amplitude-control input for receiving an amplitude-control bit, a phase-control input for receiving a phase-control bit, a signal input for receiving an input signal, a modulator for producing an output signal based on the amplitude-control bit, the phase-control bit, and the input signal, and an signal output for transmitting the output signal to the combiner. The combiner combines the two output signals from the first and second pair of elements to produce an output signal for the circuit to be transmitted by the signal output of the circuit.

Direct mm-wave m-ary quadrature amplitude modulation (QAM) modulator operating in saturated power mode

In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.

Clock and data recovery (CDR) using phase interpolation

In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.

Sequential-write, random-read memory

A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal.

Frequency synthesizer tuning

Systems and methods are provided for facilitating baseball strike zone detection. In accordance with one aspect of the present disclosure, a method includes transmitting radar pulses by a phased-array of transmitting antennas in a radar beam pattern, detecting reflected radar pulses of the transmitted radar pulses at multiple receiving antennas, calculating multiple positions of a projectile based on detecting the reflected radar pulses, determining whether an incursion through a three-dimensional strike zone characterized by batter-specific settings has occurred based on the multiple positions, and providing an indication of the incursion determination for presentation to a user.

Baseball strike zone detection radar

A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

Transition-based macro-models for analog simulation

In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.

Algorithmic matching of a deskew channel

In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.

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Los Gatos, CA, United States of America

William Warren Walker