Hughes Aircraft Company

Hughes Electronics Corporation

William W Hooper

Michael G Case

William E Stanchina

Authi Ariamuthu Narayanan

Chanh N Nguyen

Madjid Hafizi

Chanh M Nguyen

A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.

High-voltage bipolar transistor utilizing field-terminated bond-pad

A doping profile is disclosed for realizing a varactor diode that exhibits a high breakdown voltage V.sub.BR, e.g.,&gt;100 volts, and a capacitance which has a bi-level characteristic. In particular, the capacitance has a C.sub.max level and a C.sub.min level. The doping profile includes two lightly doped regions and, between them, a third region with higher doping. The doping concentrations and widths of the first two regions substantially set the tuning ratio of C.sub.max /C.sub.min, and the doping concentration and width of the third region substantially sets the transition voltage V.sub.TR between the bi-level capacitances.

Process tolerant, high-voltage, bi-level capacitance varactor diode

A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.

Reduction of base-collector junction parasitic capacitance of

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Westlake Village, CA, United States of America

William W Hooper