Advanced Micro Devices Corporation

William W Freitag, Jr

Daniel B Reents

A system and method are presented for digital communication via a time division multiplexed serial data stream. A serial communication system according to the present invention includes a serial communication controller having a set of functional units each configured to perform a specific function of a serial communication protocol. The functional units are operably coupled in series in order to produce digital data according to the serial communication protocol. The set of functional units operates alternately upon an active one of the multiple serial data channels within the time division multiplexed serial data stream. Each functional unit may be a state machine including one or more programmable registers for storing state information which determines the operating state of the functional unit. An active channel transition from a first data channel to a second data channel may be accomplished by saving state information associated with the first data channel and 'restoring' saved state information associated with the second data channel. A memory unit coupled to each functional unit may include a separate portion allocated to each of the multiple serial data channels. State information may be retrieved from the functional units and stored in the portion of the memory unit allocated to the first data channel. State information may then be retrieved from the portion of the memory unit allocated to the second data channel and stored within the memory elements of the functional units, thus accomplishing the state 'restoring' activity.

System and method for digital communication via a time division multiplexed serial data stream

A network interface unit is presented including a microcontroller having multiple blocks of programmable logic that are variably configurable to perform selected functions. The network interface unit may be configured to assemble, transmit, and receive data units (i.e., frames) of one communication protocol, then later reconfigured to assemble, transmit, and receive frames of another protocol. The microcontroller includes several components formed upon a single monolithic semiconductor substrate, among them an execution unit. The execution unit includes a processor core and multiple configurable logic blocks (CLBs) coupled to the processor core. The processor core is configured to execute instructions, for example x86 instructions. Each of the multiple CLBs includes programmable logic which may be, for example, PLA circuitry, PAL circuitry, or FPGA circuitry. The programmable logic includes programmable switching elements such as, for example, EPROM elements, EEPROM elements, or SRAM elements. During instruction execution, the processor core produces output signals. During a programming operation, the output signals include programming signals which configure the programmable logic within one or more of the multiple CLBs to perform selected functions. Once programmed, each CLB performs the selected function in response to output signals produced by the processor core. The network interface unit also includes one or more memory devices and an electrical interface unit. The one or more memory devices store instructions and data used by the processor core. The electrical interface unit is adapted for coupling to the network transmission medium and performs as an interface between the microcontroller and the network transmission medium.

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions

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Austin, TX, United States of America

William W Freitag, Jr