Qlogic Corporation

William W Dennin

Theodore Curt White

Gary S Dickinson

In a controller integrated circuit, which controls the operation of a peripheral storage device, a transfer monitoring circuit that facilitates the monitoring of successful transfers from outside the controller integrated circuit. The circuit includes a counter circuit that counts the number of successful transfers, a value storing register, a comparison circuit to compare the counter value to the value stored in the register and generate a result. The transfer monitoring circuit speeds up the operation of the controller integrated circuit especially during recovery from error conditions. The monitoring circuit also allows for a more optimal use of a look-ahead cache.

Circuit and method for monitoring sector transfers to and from storage medium

The present invention is related to methods and systems for context switching within a disk controller, allowing controller processors to efficiently switch between multiple tasks. In a first mode, a first memory is used to temporarily store data being transferred between a disk storage device coupled to the disk controller and a bus coupled to the disk controller. The transfer is managed by a disk controller processor. A first context is stored in a second memory coupled to the disk controller processor. In a second mode, the first memory is used to store a second context for later use by the disk controller processor. At least a portion of the first context information stored in the second memory is swapped with at least a portion of the second context information stored in the first memory at least partly in response to a first event. The swapped portion is then swapped back to the second memory in response to a second event.

Methods for context switching within a disk controller

The present invention is related to systems and methods for a disk controller memory. In one embodiment, a mass storage device is interfaced to a computer via an I/O bus using a mass storage device controller. The mass storage device controller includes a processor and a buffer memory configured to receive data from the mass storage device and the I/O bus. In addition, the controller includes a memory circuit coupled to the buffer memory and the processor. The memory circuit is configured to operate as a first-in-first-out memory during at least a first transfer of data between the memory circuit and the buffer memory. For example, the memory may be configured to operate as either as a random access memory or a FIFO during at least a first transfer of data between the memory circuit and the processor.

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Lake Forest, CA, United States of America

William W Dennin