Raytheon Company

Hughes Aircraft Company

William W Cheng

Lloyd Frederick Linder

Erick M Hirata

Benjamin Felder

Don C Devendorf

Kenneth Alan Essenwanger

Clifford W Meyers

Michael H Liou

Michael F Clingempeel

Robert Tso

William J Rinard

A current switching cell for a digital to analog converter. The switching cell includes three stages, a first control stage, a data stage, and a second control stage. The first control stage is configured to either disconnect the outputs of the digital to analog converter, or to connect them to the outputs of the data stage. The data stage is configured to operate in one of two states, depending on a data signal received, and the second control stage is configured to selectively invert the output of the digital to analog converter. The two control stages may be driven with several combinations of control waveforms to implement a non return to zero mode, a return to zero mode, inverse non return to zero mode, and inverse return to zero mode.

Wideband multi-mode current switch for digital to analog converter

A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Multi-mode analog to digital converter

An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) ( ) with a novel active offset method for comparators. The novel ADC architecture ( ) includes a first circuit ( ) for receiving an input signal; a second circuit ( ) for setting a predetermined number of thresholds using a predetermined number of preamplifiers ( ) with weighted unit current sources ( ) in each of the preamplifier outputs; and a third circuit ( ) for comparing the input to the thresholds. In the preferred embodiment, the ADC ( ) includes trimmable current sources ( ). The ADC ( ) of the present invention also includes an improved comparator circuit ( ). The novel comparator ( ) includes split load resistors, pairs R (active mode) and R and pairs R (active mode) and R , to increase the acquisition time and reduce the regeneration time constant, emitter follower buffers Q and Q on the latch pair transistors Q and Q to reduce the capacitive loading on the regeneration node, and cascode transistors Q and Q coupled to the load resistors to eliminate the output loading effects from the regeneration node. In the preferred embodiment, the invention also includes a novel DDS/DAC architecture ( ) with digitally trimmed unary currents and a novel sine lookup and decoder design which overcomes the conventional dynamic range limitations at high conversion rates.

Advanced digital antenna module

A high-performance delta sigma analog-to-digital converter. The high-performance delta sigma analog-to-digital converter includes a first mechanism for converting an input analog signal to a digital output signal. The first mechanism is characterized by a transfer function that is altered relative to an ideal transfer function. A second mechanism compensates for the alteration in the transfer function via a single additional digital-to-analog converter. In a specific embodiment, the alteration includes an additional pole and an additional zero induced by feedback delays in the first mechanism. The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism includes an additional latch that compensates for the signal dependent jitter delay. The first mechanism includes a resonator and a quantizer. The second mechanism includes a feedback path from an output of the quantizer to the resonator. The feedback path includes a first latch positioned between an output of the quantizer and the additional digital-to-analog converter. The additional latch is positioned at an output of the first latch and eliminates signal dependent jitter delay in the analog-to-digital converter. The additional feedback digital-to-analog converter is a non-return-to-zero digital-to-analog converter, an output of which is connected to the resonator.

Excess delay compensation in a delta sigma modulator analog-to-digital converter

A continuous time Bandpass Delta Sigma (&Dgr;&Sgr;) Modulator architecture with feedforward and feedback coefficients to completely specify both the signal transfer function (STF) and the noise transfer function (NTF) for a stable modulator ADC system.

Continuous time bandpass delta sigma modulator ADC architecture with feedforward signal compensation

A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.

Monolithic circuit and method for adding a randomized dither signal to

A sample and hold circuit uses a Class AB amplifier architecture rather than a diode bridge in a sampling gate. Input and output transistor pairs (Q5, Q6; Q7, Q8) receive an input voltage (Vin) and provide at an output terminal (6) (a) an output voltage that tracks the input signal, and (b) a current from a load dependent current source (Vcc, Vee). The output current used to charge a sample holding capacitor (Ch) is not limited to the input standing current, and operates with a lower quiescent power consumption and better distortion than prior circuits. Complementary bipolar transistors (Q15, Q16, Q17, Q18; Q9, Q10, Q11, Q12) are used in a clock driver circuit and in the sampling gate to compensate for the different operating speeds of the npn and pnp transistors.

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Redondo Beach, CA, United States of America

William W Cheng