Altera Corporation

William W Bereza

Rakesh H Patel

Shoujun Wang

Tad Kwasniewski

Haitao Mei

Sergey Yuryevich Shumarayev

Mohsen Moussavi

Tim Tri Hoang

Yuming Tao

Wilson Wong

Ping Xiao

Albert Vareljian

Weiying Ding

Mirza Baig

Chong H Lee

Thungoc M Tran

Hong Shi

Henry Y Lui

Arch Zaliznyak

Charles E Berndt

Miao Li

Muhammad Usama

Apparatus and methods are described for space-efficient, high-speed data communications for integrated circuits. Bandwidth is multiplied by using multiple individual wireline communications channels coupled to form a communications lane. The data receiver for a channel implements symbol-rate equalization and crosstalk filtering that is space efficient, allowing high-speed data communications to be added as an ancillary function to an IC.

Self-tuning high speed transceiver for IC wireline channel

An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.

Thermometer-code-to-binary encoders

Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

Digital equalizer for high-speed serial communications

Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

Charge pump with reduced current mismatch

A digital loop filter includes a fine control circuit and a coarse control circuit. The fine control circuit adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal. The coarse control circuit adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal. The second phase adjustment is larger than the first phase adjustment. The second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal.

Techniques for digital loop filters

Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements. One or more of the voltage-controlled oscillators may be implemented using a separate integrated circuit connected using through-silicon vias.

Phase-locked loop circuitry with multiple voltage-controlled oscillators

An integrated circuit (IC) includes a reference circuit. The reference circuit includes at least one controlled current source. The reference circuit further includes a sigma-delta modulator coupled to the at least one controlled current source.

Apparatus and associated methods for generating reference signals

Oscillator circuitry is provided that is based on a ring of inverters. The ring of inverters may be single-ended or differential inverters. Digitally controlled adjustable load capacitors may be provided at inverter outputs to tune the oscillator circuitry. Each digitally controlled adjustable load capacitor may be formed from multiple varactors connected in parallel. Each varactor may have a control input that receives a digital control signal. The digitally controlled adjustable load capacitors in a given oscillator may be adjusted in unison to produce the same capacitance value for each capacitor or may be adjusted individually so that they produce different capacitance values. The inverters may include common-mode-gain reduction features such as series-connected current sources, series-connected resistors, and cross-coupled negative feedback transistors.

Digitally controlled oscillators

Methods and circuits are provided for producing phase-adjusted pre-emphasis and equalization. In applications in which little or no phase distortion occurs during signal transmission, propagation, or reception, linear-phase pre-emphasis or equalization can be used to reduce or eliminate phase distortion introduced by the pre-emphasis or equalization. Linear phase, constant group delay FIR filters or circuits may have odd numbers of coefficients symmetrical about the middle coefficient. In applications in which signal phase distortion occurs, linear phase or non-linear phase pre-emphasis or equalization can be used to reduce or compensate for the phase distortion. Phase compensation may be effected using FIR pre-emphasis and equalization filters and circuits. Non-linear phase FIR filters may have different numbers and combinations of coefficients.

Phase-adjusted pre-emphasis and equalization for data communication

A wirebond package configured to reduce wirebond return loss is presented. An integrated circuit of interest with rows of bonding pads is bonded to a surface of the wirebond package. The surface of wirebond package has columns of bonding pads, which are configured to transmit or receive signals, power, and ground to and/or from the wirebond package to the integrated circuit. Corresponding die pads on the integrated circuit and bonding pads of the wirebond package are coupled using conductive lines. The conductive lines carrying the active signal has coplanar adjacent ground lines on opposing sides of active signal line and the distance between active signal line and the coplanar adjacent ground lines is tapered.

Return loss techniques in wirebond packages for high-speed data communications

A programmable logic device ('PLD') or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop ('PLL') circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.

Clock signal circuitry for multi-channel data signaling

Systems and methods for accurately and quickly simulating link performance of a transceiver operating with any given transmission medium are provided. Accurate and quick link simulations may be provided using a link simulation platform. The link simulation platform may simulate link performance using transceiver behavioral models (e.g., transmitter and receiver behavioral models) that incorporate silicon level parameters, which parameters enable the behavioral models to substantially emulate the actual behavior of the transceiver portions of the link.

Systems and methods for simulating link performance

An all-digital serializer-de-serializer includes an all-digital clock multiplier unit (CMU) circuit, an all-digital clock and data recovery (CDR) circuit, a multiplexer (MUX), and a demultiplexer (DeMUX). The all-digital clock and data recovery (CDR) circuit couples to the all-digital clock multiplier unit (CMU) circuit. The multiplexer (MUX), couples to all-digital clock multiplier unit (CMU) circuit, and serializes data. The demultiplexer (DeMUX), couples to the all-digital clock and data recovery (CDR) circuit, and de-serializes data.

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Nepean, Canada

William W Bereza