International Business Machines Corporation

Cadence Design Systems, Inc.

William Vincent Huott

Pradip Patel

Daniel Rodko

Adam J McPadden

Anuwat Saetow

David D Cadigan

Franco Motika

Mary Prilotski Kusko

Timothy Gerard McNamara

Thomas J Knips

K Paul Muller

Yuen H Chan

Kevin W Kark

Donald W Plass

Gary A Tressler

Leendert M Huisman

Uma Srinivasan

James Douglas Warnock

David S Wolpert

John Greg Massey

David L Rude

Chandrasekharan Kothandaraman

Steven Michael Douskey

Tin-Chee Lo

Norman Karl James

Ryan Andrew Fitch

Richard Frank Rizzolo

Timothy J Koprowski

Charlie Chornglii Hwang

Stephen Wu

Christopher Raymond Conklin

Bryan L Mechtly

Leah M Pfeifer Pastel

Tom Y Chang

Timothy John Slegel

Christian Jacobi

Chung-Lung K Shum

Peilin Song

Gary A Van Huben

Rolf Sautter

Samuel R Connor

Michael Cracraft

Andrew A Turner

Ricardo H Nigaglioni

Bryan J Robbins

Philip George Shephard, Iii

Maroun Kassab

Luiz Carlos Alves

Sean Michael Carey

Hagen Schmidt

William J Clarke

Ulrich Baur

Samir Kirit Patel

Robert C Redburn

Louis L Hsu

Alper Buyuktosunoglu

Sang Hoo Dhong

John Atkinson Fifield

Brian Robert Prasky

Kirk David Peterson

Anthony Saporito

Patrick James Meaney

Kyu-hyoun Kim

Michael Richard Ouellette

Wayne Frederick Ellis

Dieter F Wendel

Juergen Pille

Phillip John Restle

Adam B Collura

Michael H Wood

David E Lackey

Frank Siegfried Lehnert

Scott Barnett Swaney

Hans-Werner Tast

Tobias Webel

Michael J Cadigan, Jr

Timothy Michael Skergan

Norbert Hagspiel

Leon Jacob Sigal

Stefan Payer

Stephen P Glancy

Michael Ju Hyeok Lee

Michael B Kugel

Robert Walter Berry, Jr

Sridhar H Rangarajan

Robert Louis Franch

Eugene R Atwood

Pawel Owczarczyk

John B DeForge

Eberhard Engler

Matthew Sean Grady

Louis Bernard Bushard

Pia Naoko Sanda

Bruce Wile

Guenter Mayer

Gulsun Yasar

Thomas S Barnett

Andrew James Bianchi

Timothy J Charest

Kevin William McCauley

A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

System testing using partitioned and controlled noise

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Method to limit the time a semiconductor device operates above a maximum operating voltage

A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.

Testing bit write operation to a memory array in integrated circuits

A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Microchip level shared array repair

Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Tunable power save loop for processor chips

A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.

Built-in self-test for bit-write enabled memory arrays

Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.

Sequential error capture during memory test

A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of LLlatches connected in a chain, each LLlatch includes an Llatch and an Llatch with the Llatch having a connected output monitored for a flip. A single Ldetect circuit exclusive OR (XOR) is connected to each Llatch. An Ldetect circuit XOR tree includes an input connected to a true output of a respective Llatch in the chain. An Lclock (LCK) trigger circuit is connected to an output of the Ldetect circuit XOR tree and is shared across each of the plurality of LLlatches for correcting bit flip errors.

Implementing dynamic SEU detection and correction method and circuit

A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.

Granular variable impedance tuning

A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

Implementing SEU detection method and circuit

Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.

Power saving scannable latch output driver

A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.

Memory device command-address-control calibration

Aspects include a computer-implemented method for scan diagnostic logic circuit insertion in a circuit design topology. A method includes evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain. The method also includes identifying one of the plurality of physical structures as a physical structure of interest, and responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.

Physically aware scan diagnostic logic and power saving circuit insertion

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a 'zero' state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the 'zero' state bit and selective transistor biasing, skews the 'zero' state bit towards the complementary &#x201c;one&#x201d; state bit. This induces an increase voltage thresholds of the identified SRAM cells.

SRAM margin recovery during burn-in

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a 'zero' state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the 'zero' state bit and selective transistor biasing, skews the &#x201c;zero&#x201d; state bit towards the complementary &#x201c;one&#x201d; state bit. This induces an increase voltage thresholds of the identified SRAM cells.

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Holmes, NY, United States of America

William Vincent Huott