Sun Microsystems, Inc.

William Van Loo

Satyanarayana Nishtala

Kevin B Normoyle

John E Watkins

Zahir Ebrahim

Leslie Dean Kohn

Louis F Coffin, Iii

William A Shannon

Joseph F Moran

Ray Cheng

William N Joy

Robert Barton Garner

A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC.sub.-- CLK) signal and a source-synchronous clock (SRC.sub.-- SYN.sub.-- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC.sub.-- SYN.sub.-- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC.sub.-- SYN.sub.-- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC.sub.-- SYN.sub.-- CLK signal. Since the source and destination subsystems are synchronized by the system clock signal, an incoming data stream can be synchronized within one system clock cycle. In one embodiment, data from two streams can be multiplexed and combined into a single data signal at the source subsystem, thereby increasing the bandwidth of the computer system to twice the frequency of the system clock generator.

Source synchronization data transfers without resynchronization penalty

Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be improved significantly by including a virtual address write back cache as one of the system elements. Data protection and the reassignment of virtual addresses are supported within such a system as well. Multiple active processes, each with its own virtual address space, and an operating system shared by those processes in a manner which is invisible to user programs. Cache 'Flush' logic is used to remove selected blocks from the virtual cache when virtual addresses are to be reassigned.

Virtual address write back cache with address reassignment and cache

A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

System level mechanism for invalidating data stored in the external

A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a 'shared' state, while the Read to Share request results in the datablock being labeled as in an 'exclusive' state.

Cache coherent computer system that minimizes invalidation and copyback

Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i.e., two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as 'Don't Cache' pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.

Growing community of inventors

Palo Alto, CA, United States of America

William Van Loo