Texas Instruments Corporation

Triquint Semiconductor Texas, Inc.

William U Liu

Darrell G Hill

Shou-Kong Fan

Timothy S Henderson

Ali Khatibzadeh

Damian Costa

Hin-Fai Chau

Mark Stephen Rodder

A MOSFET (,) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (,) is located adjacent a gate structure (,). The first layer (,) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (,) comprises a second, different material (e.g. Si). The material of the barrier layer (,) is chosen to provide an energy band barrier between the raised source/drain region (,) and the channel region (,).

Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region

A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.

Method of fabricating a bipolar transistor

A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).

Lateral MOSFET having a barrier between the source/drain region and the

In one form of the invention, an emitter structure for a bipolar transistor is disclosed. The structure is comprised of an emitter layer 6 of Al.sub.x Ga.sub.1-x As, where x&gt;0.4, abutting a base layer 8.

Microwave heterojunction bipolar transistors with emitters designed for

Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

Thermally uniform transistor

The invention described herein includes, in one of its forms, a method for fabricating a semiconductor device having ledge material (148, 150, 152, 162) extending over an undercut region. The method comprises the step of forming a layer of material 164 in tensile stress over the undercut region, or region to be undercut. The layer of material in tensile stress can be a dielectric, such as silicon nitride, and provides support for the ledge material in subsequent processing steps.

Method for the fabrication of bipolar transistors

Generally, and in one form of the invention, a multiple layer wide bandgap collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.

Multiple layer wide bandgap collector structure for bipolar transistors

In one form of the invention, a bipolar transistor is disclosed, the transistor comprising a GaAs substrate in the (111) orientation 100, and an InGaAs region 106 over the substrate 100, the InGaAs region 106 having a first surface and a second surface, wherein the mole fraction of In in the InGaAs region 106 varies from said first surface to said second surface.

Method for fabricating a bipolar transistor

Bipolar transistor

Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

Generally, and in one form of the invention, a method is disclosed for reducing base-to-emitter leakage in a bipolar transistor having an active region 22 bounded by an isolation implant boundary 24, said method comprising arranging an emitter contact 26 and a base contact 36 such that at a crossing of the contacts over the implant boundary, a leakage current between the contacts along the boundary is limited by a necessity to transit the thickness of a layer of material, and whereby said transistor exhibits improved gain, noise performance, and reliability.

Method to reduce emitter-base leakage current in bipolar transistors

Method for fabricating microwave heterojunction bipolar transistors with

In one form of the invention, a method is disclosed for removing portions of successive layers of GaAs 34 and GaInP 32 comprising the steps of: performing an anisotropic reactive ion etch on the GaAs layer; and performing an isotropic wet etch on the GaInP layer, whereby a mesa formed as a result of the reactive ion etch and the wet etch has substantially vertical sidewalls, and further whereby GaInP/GaAs structures having dimensions of less than approximately 3.0 .mu.m may be fabricated.

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Dallas, TX, United States of America

William U Liu