Advanced Semiconductor Engineering, Inc.

International Business Machines Corporation

William Tze-You Chen

Su Tao

Ho-Ming Tong

Chun-Chi Lee

Po-Jen Cheng

Chih-Huang Chang

Jeng-Da Wu

Michael A Gaynes

Eric A Johnson

Bernd Karl Appelt

Wen-Pin Huang

Tien Y Wu

An optical semiconductor package includes a substrate, a chip, a plurality of bonding wires, a window, a supporter, and an encapsulant. The chip is disposed on the substrate and has an optical element. The bonding wires are used for electrically connecting the chip to the substrate. The window is supported on the supporter and positioned over the optical element of the chip. The encapsulant is overmolded on the substrate for fixing the window and encapsulating the chip and the bonding wires.

Overmolded optical package

An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 &#x3bc;m to about 8 &#x3bc;m.

Under-bump-metallurgy layer for improving adhesion

A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 &#x3bc;m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

Bump and fabricating process thereof

An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable layer over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.

Under-ball-metallurgy layer

A semiconductor package arrangement and, more particularly, a light weight and miniaturized electronic package or module, wherein the dimensions between an integrated circuit comprising a semiconductor chip and those of a chip carrier have been optimized in order to provide for minimum weight and size relationships. Furthermore, disclosed is a method of forming the semiconductor package arrangement so as to produce a small, lightweight and essentially miniaturized chip-sized chip carrier package module. The chip carrier, which may be an organic laminate, multi-layer ceramic substrate or flexible substrate, as required by specific applications, is basically designed to possess overall smaller peripheral dimensions than those of the integrated circuit or semiconductor chip which is adapted to be mounted thereon. In essence, the chip carrier or substrate is electrically connected to the semiconductor chip through the intermediary of either solder bumps or a conductive adhesive, or other suitable flip chip connection methods. The utilization of an electronic package arrangement which comprises the mounting of a chip on a chip carrier or substrate, wherein the latter is of smaller peripheral dimensions than the semiconductor chip, and thereby eliminates in particular the edge stresses generated by the differentials in thermal expansion between the chip and chip carrier substrate, and in effect, reducing the previously generally encountered high mechanical stresses and extensive heat-induced warpage leading to potential failure of the electrical interconnects or solder joints.

Miniaturized chip scale ball grid array semiconductor package

A chip package includes a die having an active surface and an inactive surface. An adhesive is formed on the inactive surface where the adhesive has a low Young's modulus of elasticity. The low Young's modulus of elasticity may be 10,000 psi or less; 1,000 psi or less; or, preferably, about 1,000 psi. Further, the adhesive may include a thermal conducting material. A protective plate is coupled to the inactive surface using the adhesive and a chip carrier is coupled to the active surface of the die.

Growing community of inventors

Endicott, NY, United States of America

William Tze-You Chen