Nvidia Corporation

William Tsu

Colyn Scott Case

William B Simms

Luc R Bisson

Ashish Kaul

David G Reed

Michael B Diamond

Barry A Wagner

Anthony Michael Tamasi

Wei-Je Robert Huang

Oren Rubinstein

Manas Mandal

Don Le

Vishal Lulla

Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

PCIE clock rate stepping for graphics and platform processors

The present invention systems and methods facilitate secure communication of information between devices. A present invention system and method can enable secure communication of proprietary content in a HDCP compliant configuration. In one embodiment, a high definition content protection key secure management method is utilized to enable efficient and secure storage of a HDCP key. A high definition content protection key value is received. The high definition content protection key is encrypted utilizing a secure key value, wherein the secure key value is not accessible via an external port. In one exemplary implementation, the secure key is stored in fuses included in a processing unit. The results of said encrypting in a memory (e.g., a BIOS memory, flash memory, etc.).

Secure information storage system and method

A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.

System and method for encoding packet header to enable higher bandwidth efficiency across bus links

A method and system for supporting multiple display interface standards are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a processing unit and a display interface. The display interface further includes a formatting logic and a set of output pins, wherein the formatting logic is configured to derive a first set of output signals conforming to a first display interface standard from a data stream, drive the first set of output signals via a set of output pins to a first display device supporting the first display interface standard, support a second display interface standard instead of the first display interface standard in response to a state change and derive the first set of output signals conforming to the second display interface standard, and drive the first set of output signals via the same set of output pins to a second display device supporting the second display interface standard.

Method and system for supporting multiple display interface standards

System and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed with a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort&#x2122; or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

Techniques for capacitively coupling signals with an integrated circuit

Circuits, methods, and apparatus that provide transactions to wake an external device from a low-power state before a data transfer. This prevents an interruption that would be caused if the external device exited the low-power state during the data transfer. One example monitors a need for data by a first device. At a predetermined time before data is needed, the first device sends a transaction to a second device. The transaction is intended to wake the second device from a low-power state. If the first device has information to indicate that the second device is not in a low-power state, this transaction can be skipped. The first device then requests data. Later transactions to the second device do not result in the second device exiting the low-power state and therefore do not interrupt or cause delays in the data transfer.

Dummy accesses to ensure CPU exits lower-power state

The present invention pertains to a computer chassis with improved airflow to reduce the occurrence of trapped air pockets and increase heat transfer from components within the chassis. The computer chassis includes a plurality of chambers, wherein each of the chambers is separated by a partition. The partitions are operable to reduce the occurrence of trapped air pockets and increase heat transfer from components of the chassis by causing air to flow through each of the chambers. The computer chassis further includes at least two air vents, wherein each of the chambers is coupled to at least one of the at least two air vents through which air enters the chamber, and wherein each of the chambers is coupled to at least one of the at least two air vents through which air exits the chamber.

Computer chassis with partitions for improved airflow

A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Asymmetrical bus for bus link width optimization of a graphics system

In a computer system employing PCI Express (PCIe) links, the PCIe bandwidth is increased by configuring an endpoint device with at least two PCIe interfaces, and coupling the first of these interfaces with a PCIe interface of a system controller and the second of these PCIe interfaces with an expansion PCIe interface of an I/O controller. Therefore, the endpoint device's performance becomes more efficient. For example, if the endpoint device is a graphics processing unit, then the endpoint device can execute more frames per second. When a read request is split up and issued as multiple read requests over the at least two PCIe interfaces, the multiple read completion packets that are received in response thereto are ordered in accordance with the timing of the multiple read requests.

Computer system having increased PCIe bandwidth

Systems and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed within a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort&#x2122; or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

System and apparatus for capacitively coupling signals with an integrated circuit

Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.

Packet combiner for a packetized bus with dynamic holdoff time

Asymmetrical bus

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

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San Jose, CA, United States of America

William Tsu