International Business Machines Corporation

Other

Google Inc.

William Thomas Flynn

Bruce Marshall Walk

Joseph Allen Kirscht

John Michael Borkenhagen

Andrew Henry Wottreng

Richard James Eickemeyer

David Alan Shedivy

Kenneth Michael Valk

Sheldon Bernard Levenstein

Dong Chen

Paul William Coteus

Alan G Gara

Todd Edward Takken

Barry Marshall Trager

Philip Rogers Hillier, Iii

James Anthony Marcella

Steven R Kunkel

Shmuel Winograd

Jack Chris Randolph

Marcy Evelyn Byers

Phillip Rogers Hillier, Iii

Troy Dale Larsen

Joesph A Kirscht

Philip Rodgers Hillier, Iii

Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at a first port of a first switch module, a packet that includes (i) path information specifying a route to the destination switch module, (ii) a set of load/store operations to be executed by the destination switch module and (iii) return path information specifying a route from the destination switch module to the source switch module. Upon determining that the first switch module is the destination switch module, the set of load/store operations are copied from the received packet into an execution buffer for automatic execution. Once the set of load/store operations are executed, embodiments transmit the packet to a second switch module using the first port on which the packet was received.

Directed route load/store packets for distributed switch initialization

Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at a first port of a first switch module, a packet that includes (i) path information specifying a route to the destination switch module and (ii) a set of load/store operations to be executed by the destination switch module. An indication of the first port is inserted into a return path information portion of the received packet. Upon determining that the first switch module is not the destination switch module, embodiments transmit the packet to a second switch module using a second port, the second port specified in the path information of the received packet, wherein the destination switch module is configured, upon receiving the packet, to copy the set of load/store operations into an execution buffer to be automatically executed.

Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments include receiving, at a first switch module, a packet that includes (i) an ordered listing of Ethernet link identifiers, specifying a path to the destination switch module and (ii) payload data to be processed at the destination switch module. Embodiments determine that the first switch module is not a destination of the packet, based on the ordered listing of Ethernet link identifiers. Additionally, an Ethernet port of the first switch module on which to transmit the packet is determined based on the ordered listing of Ethernet link identifiers. Embodiments then transmit the packet to a second switch module using the determined Ethernet port of the first switch module.

Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at the source switch module, from the destination switch module, path information specifying a path from the source switch module to the destination switch module. Upon detecting an occurrence of a predefined event, a packet is generated that includes (i) the received path information and (ii) payload data to be processed at the destination switch module. Embodiments determine an Ethernet port of the source switch module on which to transmit the packet, based on the received path information. The packet is transmitted to a second switch module using the determined Ethernet port.

Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments include determining, at the destination switch module, a path from the source switch module to the destination switch module. Path information specifying the determined path from the source switch module to the destination switch module is transmitted from the destination switch module to the source switch module. Additionally, embodiments include receiving, at the destination switch module, from the source switch module, a packet that includes (i) at least a portion of the path information and (ii) payload data to be processed at the destination switch module, wherein the packet was routed using the at least a portion of the path information. The payload data within the received packet is processing by the destination switch module.

Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments retrieve path information specifying a route to the destination switch module. A packet is created that includes (i) at least a portion of the path information and (ii) a set of load/store operations to be executed by the destination switch module. Embodiments then transmit the packet to a first switch module using a first port, the first port specified in the retrieved path information. The first switch module is configured to transmit the packet based on the at least a portion of the path information in the packet, and the destination switch module is configured, upon receiving the packet, to copy the set of load/store operations into an execution buffer to be automatically executed.

In a first aspect, a first cryptography method is provided. The first method includes the steps of (1) in response to receiving a request to perform a first operation on data in a first memory cacheline, accessing data associated with the first memory cacheline; (2) performing cryptography on data of the first memory cacheline when necessary; and (3) speculatively accessing data associated with a second memory cacheline based on the first memory cacheline before receiving a request to perform an operation on data in the second memory cacheline. Numerous other aspects are provided.

Cryptography methods and apparatus used with a processor

A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.

Using variable length packets to embed extra network control information

A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are provided. Each interconnect chip includes an ECID for the interconnect chip, each ECID is unique and is permanently stored on each interconnect chip. Each interconnect chip sends predefined exchange identification (EXID) messages including the ECID across links to other interconnect chips in the interconnect system. Each interconnect chip compares a received EXID with a system list for the interconnect system to verify validity of the sending interconnect chip.

Implementing electronic chip identification (ECID) exchange for network security

A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Implementing ordered and reliable transfer of packets while spraying packets over multiple links

A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

Error correcting code with chip kill capability and power saving enhancement

A glove dispensing system includes glove bearing sheets and a glove opening mechanism. In use, the glove dispensing system opens a cuff end of the gloves carried by the glove bearing sheets and presents the open gloves to a user. As such, the glove dispensing system provides the user with a substantially sterile glove in a manner that allows the user to easily don the gloves while limiting a risk of the user contaminating an exterior surface of the glove by touching with his hands or other body parts. In one arrangement, the gloves are integrally formed as part of the glove bearing sheets, such as by a heat-sealing process. The gloves can include coupling mechanism that secures the gloves to the glove bearing sheets and that allows ease of removal of the gloves from the glove bearing sheets after being donned by the user by a user.

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Rochester, MN, United States of America

William Thomas Flynn