Lucent Technologies Inc.

Agere Systems Inc.

Medility LLC

Agere Systems Guardian Corp.

William Thomas Cochran

Sailesh Chittipeddi

Yehuda Smooha

Isik C Kizilyalli

Morgan J Thoma

Ya-Hong Xie

Seungmoo Choi

Scott Wayne McLellan

Shahriar Moinian

Nathan R Belk

Stephen Arlon Meisner

Mark Richard Pinto

Kwok K Ng

Kang W Lee

Michel Ranjit Frei

Cheryl Anne Bollinger

Daniel Mark Wroge

David Clayton Goldthorp

Stephen Knight

Gerard Zaneski

Sensors, apparatus, and methods for measuring movements are disclosed. The sensors include input and output windings wound about a common location and an armature is equally positioned relative to both windings movable to vary inductance reactance of the sensor. The mass of the sensor and the ease of movements are such that flexible membranes, such as skin, can be monitored with insignificant interference. The sensor can be included in 'Band-aid' bandage arrangement in which the bandage backing can be removed and held in place on skin by the bandage. A monitoring circuit, responsive to the changes in sensor impedance, provides indications of the detected movements. The monitoring circuit includes an arrangement for self-adjusting parameters so that the system can be automatically preset and continually reset. The monitoring circuit includes a power savings arrangement.

Sensors for monitoring movements, apparatus and systems therefore, and methods for manufacturing and use

A generally planar shaped inductor is disclosed that is particularly adaptable for use in motion or position sensors. One inductor can function as a signal input unit and another as a pick up unit in an arrangement wherein both inductors are placed in a generally parallel juxtaposition for flux flow there between. A movable armature is located between the inductors to control the amount of flux transmission between inductors. The position of the armature relative to the inductors controls the output signal generated by the pickup inductor that are adapted to be converted into indications of displacements.

Sensor inductors, sensors for monitoring movements and positioning, apparatus, systems and methods therefore

Sensors for monitoring movements, apparatus and systems therefor, and methods for manufacture and use

A bandage type sensor arrangement wherein the sensor includes two parts movable with respect to each other, a carrier assembly is connected to the sensor parts for maintaining the sensor parts in place prior to use, and that is readily detachable for releasing the sensor parts while providing a connection of the sensor parts to a surface to be monitored. A cover is included as part of the carrier assembly to protect the operation of the sensor.

Bandage type sensor arrangement and carrier assembly therefore, and method of manufacture

A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.

Multiple purpose reticle layout for selective printing of test circuits

A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.

Dual damascene bond pad structure for lowering stress and allowing circuitry under pads

The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Method for fabricating a merged integrated circuit device

An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

Integrated circuit including ESD circuits for a multi-chip module and a method therefor

A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.

Process for forming a dual damascene bond pad structure over active circuitry

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

In a method of incorporating BIST (built-in self test) circuitry in an integrated circuit, at least one metal layer is arranged to relieve stress in the substrate under bond pads from wire attachment to these pads. By providing at least one stress relieving metal layer, which can be incorporated into electrical paths of the bond pads and related circuitry, BIST circuitry can be provided, at least partly, in the conventionally non-active semiconductive portion of the substrate under the bond pad. The method allows BIST circuitry to occupy conventionally non-active areas under the bond pads wherein leakage current from stress cracks in dielectric layers under the bond pads can be redirected to a metal layer.

Method of manufacture for an integrated circuit having a BIST circuit

A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.

Integrated circuit with twin tub

The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint. However, in a more advantageous embodiment, the bond pad footprint overlays a substantial portion of the metal layer footprint and the BIST footprint.

Device and method of manufacture for an integrated circuit having a BIST

A logic gate arrangement for switching voltages greater than the gate breakdown voltage of the transistors in the gate. Two transistors of different conductivity types, are disposed between the N and P transistors which perform the logic function of a conventional CMOS gate. The gates of the two transistors are connected to a first voltage that is less than the breakdown voltage of the transistors, with the entire logic gate being supplied with a voltage that is greater than the first voltage. Three outputs are provided, two with limited voltage swings that drive other like gates or conventional CMOS gates and the other output having a full voltage swing. Logic gates implementing various logic functions, such as NAND and NOR, are disclosed. Further, a cross-coupled logic gate is disclosed which can operate as a latch or as a logic voltage translator circuit.

Growing community of inventors

Clermont, FL, United States of America

William Thomas Cochran