Sun Microsystems, Inc.

Oracle America, Inc.

Other

William T Zaumen

Marcelino M Dignum

Jochen Behrens

Wayne F Seltzer

John P Petry

Biswadeep Nag

Santiago Martin Pericas-Geertsen

Shimon Muller

Jose Joaquin Garcia-Luna-Aceves

Ariel Hendel

David G Robinson

Louise Y Yeung

J Joaquin Garcia-Luna-Aceves

Leo A Hejza

Donald L Hoffman

Shree Murthy

Andy A Poggio

A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.

Method and apparatus for hardware XML acceleration

A system and method for load-balancing routing of a computation within a multiprocessor system. The computation includes multiple branches of execution, not just a linear sequence of steps, and thus cannot be efficiently routed by existing minimum-delay routing schemes. The cost of a single step of the computation is calculated, possibly using a ratio of outgoing data rates from the step to the incoming data rate. That cost may then be scaled for different branches of execution of the computation leading to or from that single step. For example, the calculated cost may be multiplied by each branch's probability of being executed.

Load balancing computations in a multiprocessor system

A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).

Hardware unit for parsing an XML document

A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to separate packets containing portions of the document, disk blocks, memory pages, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.

Method and apparatus for virtualized XML parsing

One embodiment of the present invention provides a system that facilitates transferring data between a data device and a data terminal across a network. The system initializes itself by establishing connections between the controller, multiplexer, and data device. The system operates by receiving a request at a multiplexer from a controller to transfer data from the data device to the data terminal. The multiplexer forwards this request to the data device that has the requested data. The multiplexer then receives a set of parameters from the data device, including the location of the outgoing data within the data device. The multiplexer moves the data from the data device into an outgoing data stream, thereby removing the necessity of first copying the data into the controller.

Method and apparatus to facilitate direct transfer of data between a data device and a network connection

A method for determining the cost of routing data is described herein, where a communication cost for routing data from a current node to a successor node over a communication channel is computed, and then a processing node cost for processing data at the current node is computed, where the processing node cost represents a ratio of data input rates to data output rates at the current node. The two computations are combined to formulate a link cost for the current node, or the cost of routing data through that node. The link cost can then be used in a routing algorithm for routing data.

Load-balanced anycasting and routing in a network

The invention generally provides for a network element and methods in the network element for allowing a matching entry in a forwarding memory to be found in a single search of the memory, for determining when an entry should be placed in the memory, and for determining when an entry should be removed from the memory, in order to make more efficient use of the fixed space available in the memory. The invention is particularly useful in making more efficient use of a Content Addressable Memory (CAM) for storing flow entries, and configuring the CAM to index an associated memory that stores forwarding and quality of service information for each CAM entry.

Management of entries in a network element forwarding memory

A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets are forwarded, if necessary given the network topology, through a separate outbound subsystem.

Routing in a multi-layer distributed network element

A system for maintaining routing tables at each router in a computer network. The system is based on (a) a feasibility condition that provides multiple loop-free paths through a computer network and that minimizes the amount of synchronization among routers necessary for the correct operation of a routing algorithm, and (b) a method that manages the set of successors during the time it synchronizes its routing-table update activity with other routers, in order to efficiently compute multiple loop-free paths, including the shortest path, through a computer network.

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Palo Alto, CA, United States of America

William T Zaumen