Marvell International Limited

Intel Corporation

William T Maghielse

Nigel C Paver

Bradley C Aldrich

Mark Norman Fullerton

Stephen J Strazdus

Mukesh Patel

Murli Ganeshan

Wing K Yu

Rupal Parikh

Jianwei Liu

Anthony Jebson

Deli Deng

Kailesh B Bavaria

According to some embodiments, a device is configured to perform a dual multiply-accumulate operation. In one embodiment, the device includes a functional unit configured to calculate, in parallel, a first multiplication product of a first coefficient and a first sample; and a second multiplication product of the first coefficient and a second sample. The first sample is an (n)th sample and the second sample is an (n+2)th sample in a plurality of sequential samples. The functional unit outputs and stores the first multiplication product and the second multiplication product in different storage locations in at least one storage device.

Dual-multiply-accumulator operation optimized for even and odd multisample calculations

According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.

Dual multiply-accumulator operation optimized for even and odd multisample calculations

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Conditional execution of coprocessor instruction based on main processor arithmetic flags

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Austin, TX, United States of America

William T Maghielse