Lam Research Corporation

William T Lee

Artur Kolics

Patrick A Van Cleemput

Yezdi N Dordi

Kaihan Abidi Ashtiani

Larry Zhao

Praveen Nalla

Derek Wong

Fritz C Redeker

Bart Jan Van Schravendijk

Michal Danek

Ramesh Chandrasekharan

Bhadri N Varadarajan

Hui-Jung Wu

David Charles Smith

Hyungsuk Alexander Yoon

Nagraj Shankar

Thomas W Mountsier

Xiaomin Bin

A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

Interlevel conductor pre-fill utilizing selective barrier deposition

Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.

Integrated direct dielectric and metal deposition

A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.

Selective formation of dielectric barriers for metal interconnects in semiconductor devices

The embodiments herein relate to methods, apparatus, and systems for forming recessed features at high aspect ratios. Often, such features are formed in the context of fabricating a vertical NAND (VNAND) memory device. Various disclosed embodiments relate to process flows that involve depositing and shaping sacrificial posts on a metal seed layer that covers an underlying stack of materials, electroplating or electroless plating metal hard mask material around the sacrificial posts, removing the sacrificial posts, and etching the underlying stack of materials to form a high aspect ratio recessed feature.

Plated metal hard mask for vertical NAND hole etch

An electronic device which in one embodiment comprises a metallization stack is provided. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited electrolessly. Additionally, the barrier metal contacts the wetting layer, where the wetting layer is wettable by solder.

Devices for metallization

A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless 'bottom up' deposition of metal is provided to fill the features.

Electroless copper deposition with suppressor

A method of filling of vias and trenches in a dual damascene structure with a filling comprising copper or copper alloy is provided. An electroless deposition filling of the vias with a via filling comprising copper or copper alloy is provided. A trench barrier layer is formed over the via filling with a trench barrier layer comprising Mn or Al. The trench barrier layer is annealed at a temperature that causes a component of the trench barrier layer to pass into the via filling. The trenches are filled with a trench filling comprising copper or copper alloy.

Interconnect with self-formed barrier

A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder.

Growing community of inventors

Dublin, CA, United States of America

William T Lee