Raytheon Company

L-3 Communications Integrated Systems L.p.

William T Jennings

Praveen S Reddy

B Scott Darnell

Bradley D Lengel

John C Hoffman

Johnathan W Craig

Colby Hoffman

Matthew C Areno

Nick Angelo

Michelle Moholt

Dache′ P Barnhart

José M Gutiérrez

Generally discussed herein are systems, devices, and methods for device verification. A method can include providing, by test equipment (TE), electrical stimulus consistent with a challenge of a challenge response pair (CRP) to a physical unclonable function (PUF) of a device under test (DUT), receiving, by the TE and from the DUT, a response to the electrical stimulus, comparing, by the TE, the provided response to responses to CRPs in a database including PUF CRPs associated with a device identification and a device type, and validating the identity of the DUT when the response of the PUF to the electrical stimulus matches the response of the CRP or invalidating the identity of the electrical device when the response of the PUF does not match the response of the CRP.

Watermarking for electronic device tracking or verification

Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

High resolution counter using phased shifted clock

A guard sensor injects a multi-GHz (multi giga-bit) guard signal along a guard signal transmission path above an observable knee in the amplitude response of the path to define a guarded region and to detect physical or electromagnetic intrusions of that guarded region. At frequencies above the knee, the signal transmission path exhibits increasingly non-linear and even chaotic behavior that improves the overall sensitivity of the sensor and its ability to detect slight changes in the distributed transmission parameters that characterize circuit devices, signal paths and signals. The guarded region may be used to protect a combination of circuit devices, physical connections, interfaces, high and low frequency signal transmission paths and signals.

Multi-GHz guard sensor for detecting physical or electromagnetic intrusions of a guarded region

A system for detecting changes to circuitry includes: a processor; and a memory, and the memory has stored thereon instructions that, when executed by the processor, cause the processor to: periodically measure physical characteristic data of the circuitry, operational data of the circuitry, and environmental data; periodically capture the measured data; generate a dynamic fingerprint based on an aggregation of a first set of the captured data, and the dynamic fingerprint is a compound data structure encapsulating the aggregated data; associate metadata with the dynamic fingerprint; periodically update the dynamic fingerprint according to successive sets of the captured data; and compare the updated dynamic fingerprint to a previous dynamic fingerprint, to detect the changes to the circuitry.

Detection system for detecting changes to circuitry and method of using the same

A system for authenticating a circuit includes: a processor; and a memory, and the memory has stored thereon instructions that, when executed by the processor, cause the processor to: periodically measure physical characteristic data of the circuit, operational data of the circuit, and environmental data; periodically capture the measured data; generate a dynamic fingerprint based on an aggregation of the captured data, and the dynamic fingerprint is a compound data structure encapsulating the aggregated data; associate metadata with the dynamic fingerprint; and output the dynamic fingerprint as a physically unclonable function (PUF) of the circuit.

Authentication system and method

This disclosure provides for implementing a firmware security interface within a field-programmable gate array (FPGA) for communicating between secure and non-secure environments executable within the FPGA. A security monitor is implemented within the programmable logic of the FPGA as a soft core processor and the firmware security interface modifies one or more functions of the security monitor. The modifications to the security monitor include establishing a timer 'heartbeat' within the FPGA to ensure that the FPGA invokes a secure environment and raising an alarm should the FPGA fail to invoke such environment.

Firmware security interface for field programmable gate arrays

According to one embodiment, an imaging system includes an interface, a plurality of filters, and a processor. The interface receives data blocks. The processor associates each data block with a processing step list that represents a filter chain that has at least a subset of the filters coupled in sequence. The processor filters each data block according to the filter chain represented by the associated processing step list.

Suppressing interference in imaging systems

According to one embodiment, generating images according to intersection points includes obtaining samples of signals from transmitter-receiver pairs. A transmitter-receiver pair is configured to transmit a signal and receive the signal reflected by an object. Intersection points are determined, where an intersection point indicates an intersection for integer multiples of a sample-time distance. A subset of samples corresponding to the intersection points is selected. Image data is generated from the selected subset of samples, where the image data is used to generate an image of the object.

Generating images according to points of intersection for integer multiples of a sample-time distance

The storage and retrieval of cryptographic key materials from a storage database utilizes a limited one-way function to create computational barriers. The limited one-way function is asymmetric in nature, in terms of work to compute and work to invert, to store and retrieve encryption keys. The limited one-way function is not intractable, but alternatively, there is some measurable difference in the amount of work required to invert a stored encryption key, compared to the work required for a calculation of the output of the one-way function for storage of an encryption key in a database.

Key escrow systems

An apparatus for scheduling transmission of a plurality of frames in a network having a plurality of nodes, each frame identified by a type designation, includes a schedule memory and a sequencer. The schedule memory stores a transmission time for each frame type and a list of frames to be transmitted. The sequencer is operable to access the schedule memory and initiate transmission of the frames in the list.

Method and system for scheduling network communication

A circuit for the implementation of modular multiplication of numbers comprises an alternative formation of the algorithm first proposed by R. C. Montgomery. The modified Montgomery algorithm is implemented in one of a plurality of circuits comprising full adders, half adders, registers and gates.

Multiplication of modular numbers

A method of managing storage of data includes assigning one of a plurality of buffer pointers to a first frame of data and storing the first frame of data in a location in memory associated with the assigned buffer pointer. The method also includes determining whether the first frame of data is associated with a sequence of frames and storing the assigned buffer pointer in a first location if the first frame of data is associated with a sequence of frames and a different location if the first frame of data is not associated with a sequence of frames. The method also includes, after storing the assigned buffer pointer, manipulating the first frame of data stored in the location in memory. The manipulation includes accessing the assigned buffer pointer.

METHOD FOR MANAGING STORAGE OF DATA BY STORING BUFFER POINTERS OF DATA COMPRISING A SEQUENCE OF FRAMES IN A MEMORY LOCATION DIFFERENT FROM A MEMORY LOCATION FOR POINTERS OF DATA NOT COMPRISING A SEQUENCE OF FRAMES

A communications system includes a plurality of network nodes including a first node having an interface unit. The interface unit includes a scheduler operable to schedule periodic transmission of a plurality of frames at respective designated times. Each of the plurality of frames includes a plurality of slots. The interface unit also includes an access system operable to designate which of the plurality of slots of a frame are accessible by each of the plurality of nodes and to access the designated slots.

Method and system for communicating information in a network

An extraction and insertion controller for inserting into and extracting data values from a frame transmitted to a plurality of nodes is provided. The frame has a plurality of slots for storing data. The insertion and extraction controller includes an access table identifying slots for extraction of information by at least one of the plurality of nodes and also identifying slots for insertion of information by at least one of the plurality of nodes. The insertion and extraction controller also includes an extraction and insertion map controller operable to control modifications to the access table and an extraction controller operable to provide data stored in one of the plurality of slots to a respective node indicated by the access table. The insertion and extraction controller also includes an insertion control unit operable to provide data to one of the plurality of slots from a respective node indicated by the access table.

Method and apparatus to insert and extract data from a plurality of slots of data frames by using access table to identify network nodes and their slots for insertion and extraction data

Growing community of inventors

Plano, TX, United States of America

William T Jennings