Intel Corporation

William T Futral

Sujoy Sen

Kenneth C Creta

Sivakumar Radhakrishnan

Gregory Cummings

Elliot D Garbus

Barry R Davis

D Michael Bell

Byron R Gillespie

Greg J Regnier

Jie Ni

David C Lee

Paul A Grun

Siva Balasubramanian

David Stewart Dunning

Ken Drottar

Thanunathan Rangarajan

Raghavendra Y K

Stanley S Amway, Iii

Ahmet D Houssein

Gregory D Cummings

Methods and apparatus are disclosed to self authorize platform code. A disclosed example apparatus to verify safety of a policy data structure (PDS) of a computing platform includes a processor and a memory including instructions that, when executed, cause the processor to, at least retrieve a hash of a PDS stored in a Trusted Platform Module (TPM), the PDS stored in the TPM at a first time and indicative of a combination of platform control registers (PCRs) to be used with the platform, calculate a hash of a PDS associated with platform update code in response to a platform code update request at a second time; and verify the hash of the PDS associated with the platform update code is safe when (a) the comparison between the hash of the PDS associated with the platform update code matches the hash of the PDS in the TPM and (b) the combination of the PCRs in the PDS stored in the TPM at the first time matches a combination of PCRs represented in the platform update code at the second time.

Methods, systems and apparatus to self authorize platform code

Methods and apparatus are disclosed to self authorize platform code. A disclosed example method includes storing a hash of a first public key in a policy data structure of a platform at a first time, extracting a second public key from a signature block associated with a data structure to be authenticated at a second time, when a hash of the second public key matches the hash of the first public key, extracting an encrypted hash from that signature block, decrypting the encrypted hash using the second public key to determine a decrypted value, and comparing the decrypted value with a hash of the data structure to verify the data structure integrity.

A data processing system may comprise a primary basic input/output system (BIOS) image in a primary BIOS region and a rollback BIOS image in a rollback BIOS region. In one example method for upgrading the BIOS, the data processing system may establish a measured launch environment (MLE). In response to a BIOS update request, the data processing system may replace the primary BIOS image with a new BIOS image while running the MLE. After a reset operation, the data processing system may automatically boot to the rollback BIOS image and may use the rollback BIOS to automatically determine whether the new BIOS image is authentic. In response to a determination that the new BIOS image is authentic, the data processing system may copy the new BIOS image from the primary BIOS region to the rollback BIOS region. Other embodiments are described and claimed.

Methods and apparatus for performing secure BIOS upgrade

Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.

Methods and apparatuses for flushing write-combined data from a buffer

A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

Stream priority

Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

Chipset feature detection and configuration by an I/O device

Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

Methodology and apparatus for implementing write combining

Machine-readable media, methods, and apparatus are described for transferring data. In some embodiments, an operating system may allocate pages to a buffer and may build a memory descriptor list that references the pages allocated to the buffer. A direct memory access (DMA) controller may process the memory descriptor list and transfer data between a buffer defined by the memory descriptor list and another location per the memory descriptor list. The DMA controller may further support data transfers that involve buffers defined by scatter gather lists and/or chained DMA descriptors built by a device driver.

Direct memory access using memory descriptor list

Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.

Readdressable virtual DMA control and status registers

An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (IO&#xae;) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the IO protocol without interrupting the host processor which normally resides on the primary PCI bus.

Accessing a primary bus messaging unit from a secondary bus through a PCI bridge

Method and apparatus for processing interrupts

In a method according to an example embodiment of the invention, a data packet is transferred from an I/O node to a host across a channel-based switching fabric interconnect. The method stores a value in a register in the I/O node which is indicative of a number of send credits available to the I/O node. The I/O node keeps a count of the number of data transfers. It is then determined from the value of the register whether or not a sufficient number of send credits is available to the I/O node for the data to be transferred by comparing it with the count of previous data transfers. If a sufficient number of send credits is available to the I/O node, it promptly transfers the data to the host over the channel-based switching fabric interconnect. If a sufficient number of send credits is not available to the I/O node, it waits for the host to update the value stored in the register before transferring data.

Register based remote data flow control

Briefly, in accordance with one embodiment of the invention, a method of processing interrupts includes the following. An interrupt status message is transmitted after detecting a change in state of an interrupt. Briefly, in accordance with another embodiment of the invention, a method of processing interrupts includes the following. After receiving an end of interrupt (EOI) signal interrupting signals until an interrupt status message indicating that the interrupt state is current is recieved.

Growing community of inventors

Portland, OR, United States of America

William T Futral