International Business Machines Corporation

William T Devine

John E Campbell

Kris V Srikrishnan

Sebastian Theodore Ventrone

Dennis T Cox

Gilbert J Kelly

John Ulrich Knickerbocker

Steven Paul Ostrander

Jeannine Madelyn Trewhella

Ronald Pete Luijten

Jeffrey Alan Kash

William F Washburn

William Gianopulos

A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.

Dynamic object-level code translation for improved performance of a computer processor

A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal semiconductor layer of an SOI substrate. A gate of the first FET overlies an upper surface of the common device layer, and a gate of the second FET underlies a lower surface of the common device layer remote from the upper surface. The first and second FETs share a common diffusion region disposed in the common device layer and are conductively interconnected by the common diffusion region. The common diffusion region is operable as at least one of a source region or a drain region of the first FET and is simultaneously operable as at least one of a source region or a drain region of the second FET.

Method and structure for buried circuits and devices

Dynamic object-level code transaction for improved performance of a computer

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

A redundant configurable VCSEL laser array optical light source which provides for integrating optical communications capabilities into manufacturing processes for a substrate or submount such as a silicon or ceramic substrate, a multi-chip module, a package board, backplane or similar component. Multiple, spatially proximate lasers and photodetectors are provided as part of an optical transmitter or receiver module to simplify assembly of the module, particularly alignment of a laser or photodetector to an optical fiber or waveguide. A feedback loop and control logic select those laser(s) or photodiodes(s) which are most strongly coupled to the transmission medium to produce the best signals. This approach greatly simplifies optical alignment, to improve yield and relax mechanical tolerances, leading to lower assembly costs and higher manufacturing yields.

Redundant configurable VCSEL laser array optical light source

A CMOS driver circuit minimizes a pass-through current flowing from a first voltage terminal to a second voltage terminal during transitions of an input signal. At least two transistors are connected in series between two voltage terminals. One transistor turns off when the input signal transitions from a low logic state to a high logic state. Another transistor turns off when the input signal transitions high-to-low. During either input signal transition, one of the transistors is off, thereby cutting the path between the voltage terminals to reduce or eliminate the pass-through current. The two transistors are controlled by the output of the circuit through a feedback loop. This feedback loop can include a delay element, one transistor controlled by a single synchronizing clock signal, or two transistors controlled by two complementary clock signals. The driver circuit can be used as a building block to provide conventional combination logic functions. Specific embodiments for an inverter and a NOR gate are described.

CMOS driver circuit for providing a logic function while reducing

This specification describes a programmable logic array (PLA) for performing logic functions on binary variables in a plurality of sequentially functioning arrays in which at least one of the arrays is conditionally powered when and only when the binary variables are supplied to the PLA in a logically useful combination.

Demand powered programmable logic array

An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.

Logical OR circuit for programmed logic arrays

This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end. The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.

High density logic array

This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.

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Ulster Park, NY, United States of America

William T Devine