Impinj, Inc.

Broadcom Corporation

Virage Logic Corporation

Synopsys, Inc.

William T Colleran

Ronald A Oliver

Christopher J Diorio

Todd E Humes

Scott A Cooper

Yanjun Ma

Ahmadreza Rofougaran

Maryam Rofougaran

Brima Babatunde Ibrahim

Stephen Wu

Meng-An Pan

Shahla Khorram

Shervin Moloudi

Ronald Lee Koepp

Jacob Jude Rael

Jay Michael Fassett

Vincent C Moretti

Hung-Ming Chien

Masood Syed

Bin Wang

Hooman Darabi

Chih-Hsin Wang

Vadim Gutnik

Aanand Esterberg

Ed Chien

Alberto Pesavento

Seth W Bridges

Shih-Hsin Wang

Jacob Rael

Methods of RFID tag assembly include affixing an antenna to an integrated circuit (IC) by forming one or more capacitors coupling the antenna and the IC with the dielectric material of the capacitor(s) including a non-conductive covering layer of the IC, a non-conductive covering layer of the antenna such as an oxide layer, and/or an additionally formed dielectric layer. Top and bottom plates of the capacitor(s) are formed by the antenna traces and one or more patches on a top surface of the IC.

RFID tag assembly methods

RFID tags are assembled through affixing an antenna to an integrated circuit (IC) by forming one or more capacitors coupling the antenna and the IC with the dielectric material of the capacitor(s) including a non-conductive covering layer of the IC, a non-conductive covering layer of the antenna such as an oxide layer, and/or an additionally formed dielectric layer. Top and bottom plates of the capacitor(s) are formed by the antenna traces and one or more patches on a top surface of the IC.

A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.

High-voltage LDMOSFET and applications therefor in standard CMOS

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Adaptive radio transceiver

Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) of a Radio Frequency Identification (RFID) tag such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, and/or a complex logic circuit function.

RFID tag with redundant non-volatile memory cell

NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Inverter non-volatile memory cell and array system

Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.

Redundant non-volatile memory cell

Systems and methods to determine timebase and timing (i.e., time sync) of received signals in RFID systems. Multiple matched filters corresponding to multiple timebases are used to receive the preambles of signals received from RFID tags. The multiple matched filters define a range of expected timebases of the received signals. The matched filter with the maximum output signal peak is used to derive the timebase and timing of the received signal. Viterbi techniques can be used in determining the timebase and timing to incorporate a portion of the data signal in addition to the preamble. Reconfigurable matched filters can be used so that after a preliminary timebase is determined as described above, the matched filters can be reconfigured to define a new smaller range centered about the preliminary timebase. This allows the timebase to be determined with finer resolution when another preamble portion is received.

RFID joint acquisition of time sync and timebase

Growing community of inventors

Seattle, WA, United States of America

William T Colleran