Leland Stanford Junior University

Maspar Computer Corporation

Maspar Computer Company

William T Blank

John R Nickolls

John Zapisek

Won Sub Kim

David M Bulfer

John M Long

Mark P McKee

To effect a block data transfer between a plurality of physical I/O devices coupled through interfaces to an I/O channel ('IOC') bus, a source logical device is established by programmably assigning to each of the physical device interfaces a logical device identifier, a leaf identifier determining when the physical device participates relative to the first data transfer in the block data transfer, a burst count specifying the number of consecutive transfers for which the physical device is responsible when its interleave period arrives, and an interleave factor identifying how often the physical device participates in the block data transfer. A destination logical device is similarly established. The source and logical devices are then activated to accomplish a block transfer of data between them. To permit different I/O processors to operate independently in making I/O requests, requests from each I/O processor are communicated to an IOC controller over another bus, which need not be a high performance bus, and are serviced to construct header packets in a transaction buffer identifying IOC transactions, including source and destination logical devices. When each packet is finished, the responsible I/O processor puts a pointer into a transaction queue, which is a FIFO register. Each IOC transaction is initiated as its corresponding pointer is popped from the transaction queue. Apparatus embodiments are disclosed as well.

Broadcasting headers to configure physical devices interfacing a data

A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.

Input/output system for parallel processing arrays

A single instruction multiple data parallel processor has a rectangular array of processing elements which is smaller than the array of data to be processed. The array of data to be processed is divided into a number of segments, each equal in size to the processing element array. Each processing element includes a memory for storing one or more data values corresponding to one data element in each of these segments of the data array. To execute an instruction on all the data, the processing elements execute the instruction on one segment of the data array at a time, repeating the process until all the data has been processed. To do this, a primary address controller generates a sequence of segment address values for each instruction to be executed. The processing elements along the periphery of the processing element array are called edge processing elements. An edge address controller generates edge address values corresponding to the segment addresses of the segments neighboring the segment currently being addressed by the primary address controller. Each processing element is coupled to its neighbors so that it can execute instructions which require access to neighboring data elements. To enable edge processing elements to access neighboring data elements, each edge processing element has special hardware for accessing data values stored in a memory location corresponding to one of the edge address values.

Virtual bit map processor

Growing community of inventors

Palo Alto, CA, United States of America

William T Blank