Sun Microsystems, Inc.

Oracle America, Inc.

Oracle International Corporation

William Stuart Coates

Robert J Drost

Ivan E Sutherland

Robert David Hopkins

Ronald Ho

Ian W Jones

Josephus Ebergen

Robert F Sproull

Robert J Bosnyak

Alex Chow

Scott M Fairbanks

Mark R Greenstreet

Charles E Molnar

David L Harris

Jon Lexau

Jo C Ebergen

Charles E Molnar, Deceased

Jon K Lexau

A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.

Equalization in proximity communication

The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.

Asynchronous FIFO circuit for long-distance on-chip communication

An integrated circuit containing a communication channel is described. This communication channel includes a transmit circuit configured to transmit signals using a voltage-mode driver, a receive circuit, and a capacitive link that couples the transmit circuit to the receive circuit. The communication channel includes a filter with a capacitive-summing junction to equalize signals communicated between the transmit circuit and the receive circuit.

Equalization in capacitively coupled communication links

A repeater circuit configured to duplicate or otherwise coordinate signal transitions between state conductors, such as for use in asynchronous communication systems. The repeater circuit may include a state node or other feature to facilitate enforcing or otherwise ordering transitioning of the state conductors.

Repeater circuit

Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

Method and apparatus for electronically aligning capacitively coupled mini-bars

The present disclosure involves reconfigurable circuits that include an asynchronous data path with asynchronous control and at least one logic element coupled with the asynchronous data path that allows the circuit to be configured to more than one logical implementation through data and control token. In one particular example, the asynchronous data path with asynchronous control includes an interconnection of memory elements, such as latches, with each memory element including a corresponding asynchronous control element, such as a GasP element. One or more logical elements are coupled at one or more points of the data path, such coupling may involve feed-back, feed-forward, or combinations of both, and may include external data connections. Through distribution of data items and control tokens to the asynchronous data path with asynchronous control, the fixed logical coupling to the data path may be reconfigured to provide various logical arrangements.

Reconfigurable circuits

One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

One embodiment of the present invention provides a system that communicates between a first semiconductor die and a second semiconductor die through optical signaling. During operation, the system converts an electrical signal into an optical signal using an electrical-to-optical transducer located on a face of the first semiconductor die, wherein the first semiconductor die and the second semiconductor die are oriented face-to-face so that the optical signal generated on the first semiconductor die shines on the second semiconductor die. Upon receiving the optical signal on a face of the second semiconductor die, the system converts the optical signal into a corresponding electrical signal using an optical-to-electrical transducer located on the face of the second semiconductor die.

Optical communication between face-to-face semiconductor chips

One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. The system then uses the clock signal to limit the maximum repetition rate of the asynchronous circuit so that only a predetermined number of asynchronous transactions may take place during each cycle of the clock signal.

Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle

One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.

Speed-matching control method and circuit

One embodiment of the present invention provides a system that facilitates asynchronously routing data within a circuit. This system includes a data destination horn, for routing data from a trunk line to a plurality of destinations. This data destination horn includes a plurality of one-to-many switching elements organized into a tree of at least one level that fans out from the trunk line to the plurality of destinations. It also includes a plurality of memory elements for storing data in transit between the plurality of one-to-many switching elements. An asynchronous control structure is coupled to the data destination horn, and is configured to control the propagation of data through the data destination horn, so that when a given data item appears at an input of a memory element, the given data item is asynchronously latched into the memory element as soon space becomes available in the memory element without having to wait for a clock signal. One embodiment of the present invention additionally includes a data source funnel, for routing data from a plurality of sources into the trunk line. This data source funnel includes a plurality of many-to-one switching elements organized into a tree of at least one level that fans in from the plurality of sources to into the trunk line. It also includes a plurality of funnel memory elements for storing data in transit between the plurality of many-to-one switching elements. Moreover, the asynchronous control structure is additionally configured to control propagation of data through the data source funnel.

Switch fabric for asynchronously transferring data within a circuit

The present invention provides a method and apparatus for data flow control. One embodiment detects input congestion and output starvation in a plurality of sub-buffers of a ripple FIFO buffer. This embodiment is used to draw conclusions about the occupancy of the ripple FIFO buffer under steady-state conditions. One embodiment detects input congestion and output starvation at every sub-buffer of the ripple FIFO buffer. Other embodiments detect input congestion and output starvation at a subset of the sub-buffers of the ripple FIFO buffer. One embodiment determines occupancy of the ripple FIFO buffer by the number of sub-buffers which report a steady congested state. Another embodiment determines occupancy of the ripple FIFO buffer by the number of sub-buffers which report a steady starved state. Another embodiment determines occupancy of the ripple FIFO buffer by the location of sub-buffers which report a steady congested state. Another embodiment determines occupancy of the ripple FIFO buffer by the location of sub-buffers which report a steady starved state. Other embodiments determine occupancy of the ripple FIFO buffer by a combination of the above methods.

Method and apparatus for data flow analysis

One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.

Method and apparatus for probing an integrated circuit through capacitive coupling

A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as &ldquo;places&rdquo; and &ldquo;paths,&rdquo; and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.

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Los Gatos, CA, United States of America

William Stuart Coates