Lenovo (singapore) Pte. Ltd.

Cadence Design Systems, Inc.

William Scott Gaskins

Jagjot Kaur

Kevin M Jackson

A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

Systems and methods for optimizing scan pipelining in hierarchical test design

Method and system for loading processor boot code from a serial flash memory device. A code fetch request is received from a processor, the code fetch request requesting a portion of boot code to be executed by the processor. The code fetch request is translated into a memory request providing random access to the serial flash memory device, and the memory request is sent to the serial flash memory. The portion of boot code is read from the serial flash memory device and provided to the processor.

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Durham, NC, United States of America

William Scott Gaskins