Other

Transmeta Corporation

Ruizhang Technology Limited Company

Ic Kinetics Inc.

William Schnaitter

Guillermo Juan Rozas

Steve Wang

James B Burr

A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Power-on reset circuit

Disclosed is a fractional bandgap circuit and method to provide a same reference voltage value in a variety of circumstances of operation, including variations in manufacturing process, temperature, and a supply voltage. The disclosed fractional bandgap circuit and method also allows for low supply voltage operation within a compact layout area.

Fractional bandgap circuit with low supply voltage and low current

A thermal sensor providing simultaneous measurement of two diodes. A first diode and a second diode are coupled to a first current source and a second current source, respectively. The ratio of the currents provided by the two sources is accurately know The voltage across each of the two diodes may be coupled to the input of a differential amplifier for determination of temperature. Alternatively, the first diode may be coupled to a first current source by a resistor with a known voltage drop, the second diode may be coupled to an adjustable second current source. The current in the second diode is equal to the sum of voltage drop across the first diode and the known voltage drop across the resistor. Under the established conditions, the Diode Equation may be used to calculate a temperature.

System for on-chip temperature measurement in integrated circuits

Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.

Signal generator with output frequency greater than the oscillator frequency

Circuitry for measuring and/or monitoring device temperature may include a first node coupled to ground, and a second node and a first resistor coupled in series to ground and in parallel to the first node. A first current driven to the first node and a second current driven to the second node can be selected such that a first voltage measured at the first node and a second voltage measured at the second node are substantially equal. The circuitry may also include a third node and a second resistor coupled in series to ground. A third current driven to the third node can be selected such that a third voltage measured at the third node is substantially equal to a reference voltage. Measures of the second and third currents and measures of the first and second resistors can be used to determine device temperature.

Systems and methods for determining device temperature

A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the NFETs. The PFETs reside in surface n-wells that are continuous with the buried n-well grid structure. The grid and n-well layout is performed on the basis of the functionality of the PFETs contained in the n-wells.

Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure

The present invention relates to the field of electronics. More particularly, forms of the present invention relate to systems, methods and circuits for generating a signal. A system, method and circuit for generating a signal are described. Forms of this system, method and circuit provide clock duty cycle improvement with no frequency reduction. Some such forms provide a clock signal approaching or achieving 50 percent with no significant frequency departure, reduction, etc. from a generated clock. One form of the present invention uses two similar clock signals that oscillate at the same frequency, but effectively inverted one from another. In one such form, the inverted signals are generated with a voltage controlled oscillator having differential stages.

System, method and circuits for generating a signal

Methods and systems for measuring temperature are described. A voltage source supplies a voltage. A current source supplies an amount of current that is controlled using a digital input signal. A diode is coupled to the current source. A comparator has a first input coupled to the voltage source and a second input coupled to a node between the current source and the diode. The digital input signal is changed to a value that causes an output of the comparator to change state. A value of the digital input signal is determined for each of two voltages. The values of the digital input signal and the two voltage values (or the difference between the two voltages) are used as inputs to a temperature calculation.

Methods and systems for measuring temperature using digital signals

A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the NFETs. At least some of the PFETs reside in surface n-wells that are continuous with the buried n-well grid structure. The grid and n-well layout is performed on the basis of the functionality of the PFETs contained in the n-wells.

A thermal sensor providing simultaneous measurement of two diodes. A first diode and a second diode are coupled to a first current source and a second current source, respectively. The ratio of the currents provided by the two sources is accurately known. The voltage across each of the two diodes may be coupled to the input of a differential amplifier for determination of temperature. Alternatively, the first diode may be coupled to a first current source by a resistor with a known voltage drop, and the second diode may be coupled to an adjustable second current source. The current in the second diode may be adjusted until the voltage across the second diode is equal to the sum of voltage drop across the first diode and the known voltage drop across the resistor. Under the established conditions, the Diode Equation may be used to calculate a temperature.

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San Ramon, CA, United States of America

William Schnaitter