Hewlett Packard Enterprise Development LP

William Scherer

Harumi Kuno

Charles Stuart Johnson

Joseph Andrew Tucek

Milind M Chabbi

Mesut Kuscu

Onkar Patil

Tuan Tran

A high performance computing system including processing circuitry and a shared fabric memory is disclosed. The processing circuitry includes processors coupled to local storages. The shared fabric memory includes memory devices and is coupled to the processing circuitry. The shared fabric memory executes a first sweep of a stencil code by sequentially retrieving data stripes. Further, for each retrieved data stripe, a set of values of the retrieved data stripe are updated substantially simultaneously. For each retrieved data stripe, the updated set of values are stored in a free memory gap adjacent to the retrieved data stripe. For each retrieved data stripe, the free memory gap is advanced to an adjacent memory location. A sweep status indicator is incremented from the first sweep to a second sweep.

Sequential memory access on a high performance computing system

Growing community of inventors

Houston, TX, United States of America

William Scherer