Hewlett-Packard Company

Hitachi, Ltd.

William S Worley, Jr

Rajiv Gupta

Frederic C Amerson

Michael S Schlansker

William R Bryg

Vinod Kumar Kathail

B Ramakrishna Rau

David V James

Alan Hersh Karp

Naohiko Irie

Rajendra Kumar

Allen Jay Baum

Jerome C Huck

David W Quint

Yooichi Shintani

Yoshikazu Tanaka

Bantwal R Rau

Terrence C Miller

Dennis Brzezinski

Michael J Mahon

David B Hollenbeck

Timothy L Michalka

Steven C Boettner

Hendrik W Nelis

Balasubramanian Kumar

Tso-Kai Liu

Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.

Package routing of integrated circuit signals

A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.

Out-of-order execution using encoded dependencies between instructions

An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.

Instruction unit having a partitioned cache

A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.

Method and system for propagating exception status in data registers and

To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Information processing apparatus with prefetch control for prefetching

A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Method and system for deferring exceptions generated during speculative

The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Vector memory operations

An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.

Computer architecture for reducing delays due to branch instructions

A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.

System for exception recovery using a conditional substitution

A gamma correction circuit in which digitized video intensity values are divided into high and low intensity ranges. Every fourth high value is gamma corrected in a lookup table and written to a frame buffer. All of the low intensity values are written to the buffer without gamma correction. The data in the buffer is mapped by a second lookup table before being converted to an analog signal. The second table maps the low intensity values to gamma corrected values and does not change the value of the high intensity values. When data is read from the frame buffer for further processing before display on a CRT, the lower intensity values need not be inverse gamma corrected. The high intensity values are inverse gamma corrected via a lookup table before such further processing.

High resolution gamma correction method and apparatus for pixel

A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

Direct input/output in a virtual memory system

Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

Cache memory consistency control with explicit software instructions

Apparatus is provided which interrupts arithmetic and logical operations defined by a major opcode instruction if the resultant overflows its defined length. One major opcode defines the arithmetic and logical operations between two operands in registers and the result, zero, one, the generated condition or first operand is stored in a register.

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Denver, CO, United States of America

William S Worley, Jr