Palo Alto Research Center Inc.

Xerox Corporation

University of California

Other

Palo Alto Research Corporation Incorporated

William S Wong

Michael L Chabinyc

Robert Anthony Street

Steven E Ready

Rene A Lujan

Sanjiv Sambandan

Alberto Salleo

Michael A Kneissl

Baomin Xu

Eugene Michael Chow

Scott Alan Elrod

Karl Anthony Littau

Steven A Buhler

Tse Nga Ng

Scott Eugene Solberg

Scott J Limb

Ana Claudia Arias

Stephen David White

Mark Teepe

Michael C Weisberg

Raj B Apte

John Stuart Fitch

Pengfei Qi

Peter Kiesel

Noble Marshall Johnson

Nathan W Cheung

Jeng Ping Lu

Thomas Hantschel

Zhihong Yang

Timothy David Sands

Christian G Van De Walle

Kateri E Paul

Robert Matusiak

Beverly Russo

Cliff Knollenberg

Christopher L Chua

Clifford F Knollenberg

David Kalman Biegelsen

Ashish V Pattekar

John E Northrup

Brent Shawhan Krusor

Jackson H Ho

Scott Jong Ho Limb

Julia Rosolovsky Greer

Scott J H Limb

Michael Yu Tak Young

Chinnwen Shih

Chinwen Shih

René A Lujan

Michael C Welsberg

Jeng-Ping Lu

JengPing Liu

Michael L Chebinyc

Mark R Teepe

A method for synthesis of silicon nanowires provides a growth reactor having a decomposition zone and a deposition zone. A precursor gas introduced into the decomposition zone is disassociated to form an activated species that reacts with catalyst materials located in the deposition zone to deposit nano-structured materials on a low melting point temperature substrate in the deposition zone. A decomposition temperature in the decomposition zone is greater than a melting point temperature of the low melting point temperature substrate. The silicon nanowire are grown directly on the low melting point temperature substrate in the deposition zone to prevent the higher temperatures in the decomposition zone from damaging the molecular structure and/or integrity of the lower melting point temperature substrate located in the deposition zone.

Growth reactor systems and methods for low-temperature synthesis of nanowires

A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.

Method of in-process intralayer yield detection, interlayer shunt detection and correction

An embodiment is a method to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern.

Laser-induced flaw formation in nitride semiconductors

Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the nanorod array. The contacts may allow I/V (current/voltage) characteristics of the nanorods to be measured.

Systems and methods for electrical contacts to arrays of vertically aligned nanorods

An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern.

A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.

Method for aligning elongated nanostructures

A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions.

Geometry and design for conformal electronics

A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

Annealing a buffer layer for fabricating electronic devices on compliant substrates

A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.

Large area electronic sheet and pixel circuits with disordered semiconductors for sensor actuator interface

A method and apparatus for using TFT transistors or MIS capacitors as light-sensing elements in charge mapping arrays. A bias stress may be applied to a plurality of pixels in a charge map array. As a result, charge carriers may be trapped in each of the plurality of pixels responsive to the bias stress, which may be observed as a value shift such as a threshold voltage Vshift. Light may then be transmitted toward the plurality of pixels in the charge map array causing some of the pixels to absorb the light. The trapped charge carriers are released in the pixels that absorbed the light and not released in the pixels that did not absorb the light. The value shift in each of the pixels can be compared to determine which of the pixels absorbed the light.

Method and apparatus for using thin-film transistors and MIS capacitors as light-sensing elements in charge mapping arrays

A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Charge mapping memory array formed of materials with mutable electrical characteristics

A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.

Structure and method for flexible sensor array

A GaN/AlN superlattice is formed over a GaN/sapphire template structure, serving in part as a strain relief layer for growth of subsequent layers (e.g., deep UV light emitting diodes). The GaN/AlN superlattice mitigates the strain between a GaN/sapphire template and a multiple quantum well heterostructure active region, allowing the use of high Al mole fraction in the active region, and therefore emission in the deep UV wavelengths.

Light emitting structure including high-al content MQWH

Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A first alignment operation is performed to achieve a specified orientation between the printhead and a first set of alignment marks on the substrate using first image data generated by the imaging sensor of the camera before performing a first print operation, and a second alignment operation to orient the printhead relative to a second set of alignment marks is performed before a second print operation. A first pattern layout portion includes first layout elements aligned parallel to a first reference axis, and the first print operation is performed by making multiple printing passes in a print direction aligned with the first reference axis.

Method for the printing of homogeneous electronic material with a multi-ejector print head

Growing community of inventors

San Carlos, CA, United States of America

William S Wong