Fairchild Semiconductor Corporation

Fairchild Camera and Instrument Corp.

National Semiconductor Corporation

William S Phy

James M Early

James W Clark

Michael Brueggeman

Harlan Lawler

Shane Harrah

Kevien J Negus

An improved tape automated bonding method of bonding the beam leads of lead frame tape to gold bumps formed on the contact pads of a semiconductor device, wherein the tape includes a plurality of interconnected beam leads defined by at least one opening in the tape such that each beam lead has an inner end and an outer end. The method includes the steps of depositing a gold layer on the beam leads, masking a region of each beam lead from further deposition of material such that a predetermined portion of each beam lead is exposed for further deposition of material, depositing a predetermined amount of tin on the exposed portion of each beam lead, establishing contact between each beam lead and the die bump to which each beam lead is to be bonded and applying a predetermined amount of pressure and heat to form a bond between each beam lead and the die bump to which the beam lead is to be bonded such that the bond formed includes the primary eutectic of the combination of tin and gold.

Gold/tin eutectic bonding for tape automated bonding process

A ceramic semiconductor package suitable for high frequency operation includes internal and external ground planes formed on opposite faces of a ceramic base member. The internal ground plane is connected to a ground ring formed on the packaged semiconductor device, and both ground planes are interconnected about the periphery of the package. In this way, a uniform and continuous ground is provided to minimize variations in signal transmission line impedance.

Ceramic package for high frequency semiconductor devices

A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads on the chip package, the lead alignment bars being formed from a material providing electrical isolation between leads during testing of the chip package and for providing physical spacing between the leads both during testing and later mounting of the chip package on the substrate so as to prevent adjacent leads from inadvertent contact. Preferably, the lead alignment bars are formed from a high resistivity material selected to provide sufficient conductivity between the interconnected leads for minimizing electrostatic discharge conditions therebetween, the material being sufficiently non-conductive to permit functional and dynamic testing of the leads. After testing of the chip package, it is mounted on the substrate with the interconnecting lead alignment bars then being removed to facilitate subsequent operation of the chip package.

Semiconductor chip package configuration and method for facilitating its

A plastic semiconductor package suitable for high frequency operation includes an internal ground plane connected to a ground ring formed on the packaged semiconductor device. The ground plane is included as a portion of a lead frame strip adjacent to the individual lead frames. The ground plane is first folded underneath the paddle support of the lead frame, and the semiconductor die subsequently mounted on the paddle. The ground plane includes a plurality of bumps which protect upward between adjacent lead fingers of the lead frame when the ground frame is folded. A ground frame on the semiconductor die is connected to the bumps, and the signal bonding pads connected to the lead fingers, typically by wire or tape bonding. The package is then encapsulated in plastic by conventional means, and the package trimmed to its final desired configuration.

Plastic package for high frequency semiconductor devices

A process for bonding silicon die to a package. This process comprises the following steps: (a) providing to the back surface of the die an adhesion layer of material which exhibits superior adhesion to both the silicon die and a subsequently applied barrier layer; (b) providing to the adhesion layer a barrier layer which is impervious to silicon; (c) providing to the barrier layer a bonding layer; and (d) bonding the die to the package by activating a binder composition disposed at the interface of the package and the bonding layer. The barrier layer prevents the migration of silicon to the bonding layer, both at the time of application of the bonding layer to the die and at the time of bonding the die to the package. The adhesion layer enhances the adhesion of the barrier layer material to the back surface of the die. Titanium is the preferred adhesion layer material while tungsten is the preferred barrier layer material. The bonding layer preferably comprises gold while the preferred binder composition is a gold-tin alloy solder. The enhanced adhesion of the barrier layer which prevents silicon migration into the gold produces highly reliable bonds. In another embodiment, a stress relief layer is interposed between the adhesion layer and the back of the silicon die. The material of the stress relief layer is alloyed to the silicon at the back surface of the die which relieves stresses in the die and enhances the planarity of the back surface. This produces bonds which exhibit superior electrical and thermal contact characteristics.

Die bonding process

A lead frame that is suited for use on array types of integrated circuit packages to provide a high degree of compliance for absorbing mechanical stress induced by thermal changes includes a series of individual terminal elements that are connected in a strip form by means of break tabs disposed between adjacent elements. Each terminal element provides two spaced, generally parallel mounting surfaces that are resiliently connected to one another by means of an integral intermediate section. While the terminal elements are interconnected in strip form, one of the mounting surfaces of each element can be bonded to an associated attachment region on the semiconductor substrate. After all of the terminals of the strip have been so bonded, the break tabs between adjacent terminals can be removed to thereby separate the terminals from one another. The package which then results contains discrete compliant terminals which are suitable for subsequent surface attachment to the printed circuit board.

Process of forming a compliant lead frame for array-type semiconductor

A semiconductor wafer having a plurality of integrated circuits is provided. One surface of the wafer includes a plurality of electrical contacts on the circuits which are subsequently attached to leads. The other surface of the wafer is provided with a conductive tape. The wafer is cut, e.g., sawed, resulting in each individual circuit having a pre-attached conductive mounting media. The individual circuits can then be attached to a substrate through the conductive mounting media. Other embodiments are disclosed.

Integrated circuit having a pre-attached conductive mounting media and

A multiple layer tape bonding technique interconnects an integrated circuit chip having signal and ground bonding pads located thereon to other electrical devices. The tape bonding structure is comprised of a first layer having electrically isolated individual signal conductors coupled to respective ones of the signal bonding pads. The individual signal conductors extend away from the integrated circuit chip in an approximately parallel-spaced relationship to one another. An electrically insulating layer having a predefined thickness is deposited atop and adjacent the first layer. A ground plane layer overlies the insulating layer. The ground plane layer is comprised of a plurality of individual ground conductors coupled to respective individual ones of the ground bonding pads of the integrated circuit chip. The individual ground conductors overlie the insulating layer in a precisely spaced parallel relationship to the corresponding individual signal conductors. The individual ground conductors can be ieither electrically commoned, or electrically isolated to allow for individual tapering for impedance matching. The signal and grounding pads on the integrated circuit chip can be positioned relative to to each other in either a parallel aligned spaced relationship or in alternating and staggered spaced relationship to each other.

Signal ground planes for tape bonded devices

An applique of a prepatterned film of alpha particle resistant material, such as polyimide, is applied to a semiconductor wafer. The prepatterned film covers only the critical areas e.g. those affected by alpha particle impingement. Bond pads and scribe streets are not covered by the applique.

Semiconductor structure having alpha particle resistant film and method

The present invention relates to a method and apparatus for forming a ball bond between a fine wire such as aluminum wire and a surface with the ball bond being approximately radially symmetric about a principal axis of a portion of the wire. The apparatus may include a plurality of electrodes radially spaced about the wire to define gaps between each electrode and the tip of the wire and a plurality of resistance elements. A voltage source may be connected to form a circuit consisting of plural electrically parallel legs, each of which includes the series combination of a resistance element, an electrode and an arc path between the electrode and the tip of the wire. A molten ball is formed at the end of the wire when arcs are essentially simultaneously produced between the electrodes and the tip of the wire. In a preferred embodiment, the resistances of the resistance elements are approximately equal. In addition, the plurality of electrodes are preferably symmetrically spaced about the wire to define gaps of nearly equal length between each electrode and the tip of the wire.

Method and apparatus for forming ball bonds

A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.

Process for fabricating precision optical spacers for image sensor

A lead frame (20) for tape automated bonding includes individual leads (12) each having a stretch loop (40) to accommodate elongation of the loop as the lead is bonded to a substrate (28) after inner lead bonds have been formed to an integrated circuit (26). Such a lead frame allows temporary connection and testing of the circuit prior to final lead formation and packaging.

Lead format for tape automated bonding

Precision optical spacers for image sensor filters

A technique is disclosed for protecting integrated circuits from alpha particles. A central portion of a radiation resistant insulating substrate upon which electrically conductive leads are disposed is positioned in proximity to the integrated circuit. When the leads are electrically connected to the integrated circuit, the central portion of the substrate is allowed to remain over the integrated circuit to protect the integrated circuit. The insulating substrate typically comprises a polyimide film resistant to alpha particles.

Radiation protection for integrated circuits utilizing tape automated

A device for forming reference axes on an image sensor package containing an image sensor array. The device comprises an optical means having a reticle formed therein, a movable table located in a plane parallel with the plane of the optical means, a scribe mounted between the movable table and the optical means and movable in a direction parallel with the reticle.

Growing community of inventors

Los Altos Hills, CA, United States of America

William S Phy