Pictos Technologies, Inc.

Ess Technology, Inc.

Elonex Technologies, Inc.

William S Jacobs

Sean R Atsatt

Pascal Dornier

William J Seiler

Dan Kikinis

Kathleen Anne Duncan

Robert G Taylor

A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.

Programmable display controller

A programmable image transform processor has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

Programmable image transform processor for digital image processing

A programmable timing generator for a digital imaging system has a first clock generator and a second clock generator. The first clock generator includes a programmable microsequencer and generates a plurality of first clock signals in response to the microsequencer. The second programmable clock generator is responsive to the microsequencer and generates second clock signals. The first clock signals have a lower frequency than the second clock signals. In a typical implementation, the second clock signals are called horizontal clock signals, which are used for clocking rows of pixel data out of a digital image sensor, while the first clock signals are called vertical clock signals that are used for shifting pixel data one position in vertical shift registers in the digital image sensor. The horizontal or vertical clock signals can also be used to control the image capture operation of the digital sensor, with the programmable microsequencer being used to control the image capture exposure time.

Programmable timing generator

A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to 'high' memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

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Santa Cruz, CA, United States of America

William S Jacobs